Datasheet SAM9X60 SIP (Microchip) - 9
| Manufacturer | Microchip |
| Description | SAM9X60 System-In-Package (SIP) MPU with up to 1 Gbit DDR2 SDRAM and up to 64 Mbits SDR-SDRAM |
| Pages / Page | 40 / 9 — SAM9X60 SIP. Block Diagram. Block Diagram Figure 4-1. SAM9X60 SIP Series … |
| File Format / Size | PDF / 770 Kb |
| Document Language | English |
SAM9X60 SIP. Block Diagram. Block Diagram Figure 4-1. SAM9X60 SIP Series Block Diagram. ARM926EJ-S. Key. PIO. Private. Key Bus. Multi-
Model Line for this Datasheet
Text Version of Document
SAM9X60 SIP Block Diagram 4. Block Diagram Figure 4-1. SAM9X60 SIP Series Block Diagram
JTAGSEL
ARM926EJ-S
TMS, TCK JTAG DDR_CAL TDI Boundary In-Circuit Emulator DDR_VREF TDO, RTCK Scan NTRST ICache DCache SDR- MMU 32 Kbytes 32 Kbytes SDRC SDRAM Bus Interface Unit + or MPDDRC DDR2-
Key
I D SDRAM (Dynamic Memory Digital Controller) Analog M M SRAM0 Memories S S PIO (64 Kbytes) EBI S Backup Area Processor and S Crypto-accelerators SRAM1 M Matrix Master S SMC (4 Kbytes) S Matrix Slave NWAIT A[20:25] M S ROM D[16:31] XDMA M (96 KB +
PIO
NCS2..5 64 KB) NANDOE, NANDWE PMECC NANDALE, NANDCLE PMERRLOC NANDCS OTP memory S OTPC (11 KB) M
Private
HS HHSDPC PC
Key Bus
USB HOST Trans HHSDMC M HS EHCI PB Peripheral M S DMA FS OHCI HS HHSDPB Bridge PA Trans HHSDMB FLEXCOM RTUNE (USART / SPI / TWI) FLEXCOMx_IO0..7 HS 4–5 & 11–12 DHSDP / HHSDPA AES (x4) M Trans HS USB DHSDM / HHSDMA DMA TF, TK
Multi-
TD SSC SHA RF, RK
Layer
RD ISI_D[11/0]
AHB
ISI_PCK M ISI DMA ISI_HSYNC, ISI_VSYNC CLASSD_L0..3 CLASSD TDES ISI_MCK Peripheral Bus 1
MATRIX
LCDDAT[23:0] LCDVSYNC, LCDHSYNC I2SMCC_MCK, I2SMCC_ DO M LCDC DMA LCDPCLK, LCDEN I2SMCC_WS, I2SMCC_CK I2SMCC TRNG LCDDISP, LCDPWM I2SMCC_DIN
PIO
M GFX2D DMA Peripheral S Bridge TC TIOAx, TIOBx 32-bit Timer E0_TXEN, E0_TXER TCLKx E0_TX[3:0], E0_MDC (x6) E0_TXCK, E0_RXCK M EMAC0 DMA E0_CRS, E0_COL, E0_RX[3:0] FLEXCOM
PIO
E0_RXER, E0_RXDV (USART / SPI / TWI) E0_MDIO FLEXCOMx_IO0..7 0–3 & 6–10 E1_REFCK, E1_RXER (x9) EMAC1 E1_TXEN, E1_TX[1:0] M E1_CRSDV, E1_RX[1:0] DMA (RMII) E1_MDIO PWM0..3 PWM E1_MDC ADVREFP, ADVREFN Peripheral Bus 0 M SDMMCx_CMD 12-bit SDMMC SDMMCx_CK AD0..11 M 12-channel DMA (x2) SDMMCx_DAT[3:0] ADTRG ADC
PIO
CANTXx CAN QSCK S QSPI QCS CANRXx (x2) QIO0..3 System Clocks System Controller Clock Generator Clock PIO Sources PIT64B WDT VDDOUT25 PLLA UPLL PMC A – D (64-b Timer) REG Main RC SLOW RC GPBR RTC / VDDIN33 DBGU AIC RSTC OSC OSC. (8 x 32) RTT POR Main XTAL 32768 Hz VDDBU VDDCORE SHDWC OSC XTAL OSC POR POR
PIO
Backup Area
PIO
XIN –1 DTXDDRXD XOUT XIN32 SHDN WKUP NRST XOUT32 EXT_FIQ EXT_IRQ PCK0 NRST_OUT WKUP1–13 © 2020 Microchip Technology Inc.
Datasheet
DS60001580B-page 9 Document Outline Scope Introduction Reference Documents Features Table of Contents 1. DDR2-SDRAM Features 2. SDR-SDRAM Features 3. Configuration Summary 4. Block Diagram 5. Chip Identifier 6. Package and Ballout 6.1. Packages 6.2. Ballout 7. Memories 8. Electrical Characteristics 8.1. Decoupling 8.2. Power Sequences 9. Mechanical Characteristics 9.1. 233-Ball TFBGA 9.2. 196-Ball TFBGA 10. Ordering Information 11. Revision History 11.1. DS60001580B - 02/2020 11.2. DS60001580A - 10/2019 The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
JTAGSEL
ARM926EJ-S
TMS, TCK JTAG DDR_CAL TDI Boundary In-Circuit Emulator DDR_VREF TDO, RTCK Scan NTRST ICache DCache SDR- MMU 32 Kbytes 32 Kbytes SDRC SDRAM Bus Interface Unit + or MPDDRC DDR2-
Key
I D SDRAM (Dynamic Memory Digital Controller) Analog M M SRAM0 Memories S S PIO (64 Kbytes) EBI S Backup Area Processor and S Crypto-accelerators SRAM1 M Matrix Master S SMC (4 Kbytes) S Matrix Slave NWAIT A[20:25] M S ROM D[16:31] XDMA M (96 KB +
PIO
NCS2..5 64 KB) NANDOE, NANDWE PMECC NANDALE, NANDCLE PMERRLOC NANDCS OTP memory S OTPC (11 KB) M
Private
HS HHSDPC PC
Key Bus
USB HOST Trans HHSDMC M HS EHCI PB Peripheral M S DMA FS OHCI HS HHSDPB Bridge PA Trans HHSDMB FLEXCOM RTUNE (USART / SPI / TWI) FLEXCOMx_IO0..7 HS 4–5 & 11–12 DHSDP / HHSDPA AES (x4) M Trans HS USB DHSDM / HHSDMA DMA TF, TK
Multi-
TD SSC SHA RF, RK
Layer
RD ISI_D[11/0]
AHB
ISI_PCK M ISI DMA ISI_HSYNC, ISI_VSYNC CLASSD_L0..3 CLASSD TDES ISI_MCK Peripheral Bus 1
MATRIX
LCDDAT[23:0] LCDVSYNC, LCDHSYNC I2SMCC_MCK, I2SMCC_ DO M LCDC DMA LCDPCLK, LCDEN I2SMCC_WS, I2SMCC_CK I2SMCC TRNG LCDDISP, LCDPWM I2SMCC_DIN
PIO
M GFX2D DMA Peripheral S Bridge TC TIOAx, TIOBx 32-bit Timer E0_TXEN, E0_TXER TCLKx E0_TX[3:0], E0_MDC (x6) E0_TXCK, E0_RXCK M EMAC0 DMA E0_CRS, E0_COL, E0_RX[3:0] FLEXCOM
PIO
E0_RXER, E0_RXDV (USART / SPI / TWI) E0_MDIO FLEXCOMx_IO0..7 0–3 & 6–10 E1_REFCK, E1_RXER (x9) EMAC1 E1_TXEN, E1_TX[1:0] M E1_CRSDV, E1_RX[1:0] DMA (RMII) E1_MDIO PWM0..3 PWM E1_MDC ADVREFP, ADVREFN Peripheral Bus 0 M SDMMCx_CMD 12-bit SDMMC SDMMCx_CK AD0..11 M 12-channel DMA (x2) SDMMCx_DAT[3:0] ADTRG ADC
PIO
CANTXx CAN QSCK S QSPI QCS CANRXx (x2) QIO0..3 System Clocks System Controller Clock Generator Clock PIO Sources PIT64B WDT VDDOUT25 PLLA UPLL PMC A – D (64-b Timer) REG Main RC SLOW RC GPBR RTC / VDDIN33 DBGU AIC RSTC OSC OSC. (8 x 32) RTT POR Main XTAL 32768 Hz VDDBU VDDCORE SHDWC OSC XTAL OSC POR POR
PIO
Backup Area
PIO
XIN –1 DTXDDRXD XOUT XIN32 SHDN WKUP NRST XOUT32 EXT_FIQ EXT_IRQ PCK0 NRST_OUT WKUP1–13 © 2020 Microchip Technology Inc.
Datasheet
DS60001580B-page 9 Document Outline Scope Introduction Reference Documents Features Table of Contents 1. DDR2-SDRAM Features 2. SDR-SDRAM Features 3. Configuration Summary 4. Block Diagram 5. Chip Identifier 6. Package and Ballout 6.1. Packages 6.2. Ballout 7. Memories 8. Electrical Characteristics 8.1. Decoupling 8.2. Power Sequences 9. Mechanical Characteristics 9.1. 233-Ball TFBGA 9.2. 196-Ball TFBGA 10. Ordering Information 11. Revision History 11.1. DS60001580B - 02/2020 11.2. DS60001580A - 10/2019 The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service
