Datasheet SAMA5D27C AUTO (Microchip) - 2
| Manufacturer | Microchip |
| Description | Ultra-low power ARM Cortex-A5 core-based MPU, 500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB, Security, Automotive |
| Pages / Page | 2554 / 2 — SAMA5D27C AUTO. Note 1: |
| File Format / Size | PDF / 8.3 Mb |
| Document Language | English |
SAMA5D27C AUTO. Note 1:
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SAMA5D27C AUTO
Wakeup from up to nine wakeup pins, UART reception, analog comparison Fast wakeup capability Extended Backup mode with DDR in Self-Refresh mode • Peripherals - LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit parallel RGB - ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface - Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D amplifier - One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch) - One Pulse Density Modulation Interface Controller (PDMIC) - One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host ports (UHPHS) - One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface - One 10/100 Ethernet MAC (GMAC) Energy efficiency support (IEEE 802.3az standard) Ethernet AVB support with IEEE802.1AS time stamping IEEE802.1Qav credit-based traffic-shaping hardware support IEEE1588 Precision Time Protocol (PTP) - Two high-speed memory card hosts: SDMMC0: SD 3.0, eMMC 4.51, 8 bits SDMMC1: SD 2.0, eMMC 4.41, 4 bits only - Two master/slave Serial Peripheral Interfaces (SPI) - Two Quad Serial Peripheral Interfaces (QSPI) - Five FLEXCOMs (USART, SPI and TWI) - Five UARTs - Two master CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-triggered transmission - One Rx only UART in backup area (RXLP) - One analog comparator (ACC) in backup area - Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I2C protocol and SMBUS (TWIHS) - Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes - One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller - One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with Resistive TouchScreen capability • Safety - Zero-power Power-On Reset (POR) cells - Main crystal clock failure detector - Write-protected registers - Integrity Check Monitor (ICM) based on SHA256 - Memory Management Unit - Independent watchdog • Security - 5 Kbytes of internal scrambled SRAM: 1 Kbyte non-erasable on tamper detection 4 Kbytes erasable on tamper detection - 256 bits of scrambled and erasable registers - Up to eight tamper pins for static or dynamic intrusion detections - Secure Boot Loader(1) - On-the-fly AES encryption/decryption on DDR and QSPI memories (AESB) - RTC including time-stamping on security intrusions - Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)
Note 1:
For secure boot strategies, refer to the document “SAMA5D2 Series Secure Boot Strategy” (document no. 44040), available under Non-Disclosure Agreement (NDA). Contact a Microchip Sales Representative for details. • Hardware cryptography - SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2 - AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197 - TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3 DS60001532A-page 2 2018 Microchip Technology Inc. Document Outline Introduction Features 1. Description 2. Configuration Summary 3. Block Diagram 4. Signal Description 5. Automotive Quality Grade 6. Safety and Security Features 6.1 Design for Safety and IEC60730 Class B Certification 6.1.1 Background Information 6.2 Design for Security 6.3 Safety and IEC 60730 Features 6.4 Security Features 7. Package and Pinout 7.1 Packages 7.2 Pinouts 8. Power Considerations 8.1 Power Supplies 8.2 Powerup Considerations 8.3 Powerdown Considerations 8.4 Power Supply Sequencing at Backup Mode Entry and Exit 8.4.1 VDDBU Power Architecture 8.4.2 Backup Mode Entry 8.4.3 Backup Mode Exit (Wakeup) 9. Memories 9.1 Embedded Memories 9.1.1 Internal SRAM 9.1.2 Internal ROM 9.1.3 Boot Strategies 9.2 External Memory 9.2.1 External Bus Interface 9.2.2 Supported Memories on DDR2/DDR3/LPDDR1/LPDDR2/LPDDR3 Interface 9.2.3 Supported Memories on Static Memories and NAND Flash Interfaces 9.2.4 DDR and SDMMC I/Os Calibration 9.2.4.1 DDR I/O Calibration 9.2.4.2 SDMMC I/O Calibration 10. Event System 10.1 Real-time Event List 10.2 Real-time Event Mapping 11. System Controller 11.1 Power-On Reset 12. Peripherals 12.1 Peripheral Mapping 12.2 Peripheral Identifiers 12.3 Peripheral Signal Multiplexing on I/O Lines 12.4 Peripheral Clock Types 13. Chip Identifier (CHIPID) 13.1 Description 13.2 Embedded Characteristics 13.3 Chip Identifier (CHIPID) User Interface 13.3.1 Chip ID Register 13.3.2 Chip ID Extension Register 14. ARM Cortex-A5 14.1 Description 14.1.1 Power Management 14.1.1.1 Run Mode 14.1.1.2 Standby Mode 14.2 Embedded Characteristics 14.3 Block Diagram 14.4 Programmer Model 14.4.1 Processor Operating Modes 14.4.2 Processor Operating States 14.4.2.1 Switching State 14.4.3 Cortex-A5 Registers 14.4.3.1 CP15 Coprocessor 14.4.4 CP 15 Register Access 14.4.5 Addresses in the Cortex-A5 processor 14.4.6 Security Extensions Overview 14.4.6.1 System Boot Sequence 14.4.7 TrustZone 14.4.7.1 Hardware 14.4.7.2 Software 14.4.7.3 Debug 14.5 Memory Management Unit 14.5.1 About the MMU 14.5.2 Memory Management System 14.5.2.1 Memory types 14.5.3 TLB Organization 14.5.3.1 Micro TLB 14.5.3.2 Main TLB 14.5.4 Memory Access Sequence 14.5.5 Interaction with Memory System 14.5.6 External Aborts 14.5.6.1 External Aborts on Data Write 14.5.6.2 Synchronous and Asynchronous Aborts 14.5.7 MMU Software Accessible Registers 15. L2 Cache Controller (L2CC) 15.1 Description 15.2 Embedded Characteristics 15.3 Product Dependencies 15.3.1 Power Management 15.4 Functional Description 15.4.1 Double Linefill Issuing 15.5 L2 Cache Controller (L2CC) User Interface 15.5.1 L2CC Cache ID Register 15.5.2 L2CC Type Register 15.5.3 L2CC Control Register 15.5.4 L2CC Auxiliary Control Register 15.5.5 L2CC Tag RAM Latency Control Register 15.5.6 L2CC Data RAM Latency Control Register 15.5.7 L2CC Event Counter Control Register 15.5.8 L2CC Event Counter 1 Configuration Register 15.5.9 L2CC Event Counter 0 Configuration Register 15.5.10 L2CC Event Counter 1 Value Register 15.5.11 L2CC Event Counter 0 Value Register 15.5.12 L2CC Interrupt Mask Register 15.5.13 L2CC Masked Interrupt Status Register 15.5.14 L2CC Raw Interrupt Status Register 15.5.15 L2CC Interrupt Clear Register 15.5.16 L2CC Cache Synchronization Register 15.5.17 L2CC Invalidate Physical Address Line Register 15.5.18 L2CC Invalidate Way Register 15.5.19 L2CC Clean Physical Address Line Register 15.5.20 L2CC Clean Index Register 15.5.21 L2CC Clean Way Register 15.5.22 L2CC Clean Invalidate Physical Address Line Register 15.5.23 L2CC Clean Invalidate Index Register 15.5.24 L2CC Clean Invalidate Way Register 15.5.25 L2CC Data Lockdown Register 15.5.26 L2CC Instruction Lockdown Register 15.5.27 L2CC Debug Control Register 15.5.28 L2CC Prefetch Control Register 15.5.29 L2CC Power Control Register 16. Debug and Test Features 16.1 Description 16.2 Embedded Characteristics 16.3 Debug and Test Block Diagrams 16.4 Application Examples 16.4.1 Debug Environment 16.4.2 Test Environment 16.5 Debug and Test Pin Description 16.6 Functional Description 16.6.1 Test Pin 16.6.2 EmbeddedICE 16.6.3 JTAG Signal Description 16.6.4 Chip Access Using JTAG Connection 16.6.5 IEEE 1149.1 JTAG Boundary Scan 16.7 Boundary JTAG ID Register 16.8 Cortex-A5 DP Identification Code Register IDCODE 16.8.1 JTAG Debug Port (JTAG-DP) 16.8.2 Serial Wire Debug Port (SW-DP) 17. Standard Boot Strategies 17.1 Description 17.2 Flow Diagram 17.3 Chip Setup 17.4 Boot Configuration 17.4.1 Boot Configuration Word 17.4.2 Boot Sequence Controller Configuration Register 17.4.3 Backup Registers (BUREG) 17.4.4 Boot Configuration Word 17.4.5 NVM Boot Sequence 17.4.6 Valid Code Detection 17.4.6.1 ARM Exception Vectors Check 17.4.6.2 boot.bin File Check 17.4.7 Detailed Memory Boot Procedures 17.4.7.1 NAND Flash Boot: NAND Flash Detection 17.4.7.2 NAND Flash Boot: PMECC Error Detection and Correction 17.4.7.3 SDCard / e.MMC Boot 17.4.7.4 SPI Flash Boot 17.4.7.5 QSPI NOR Flash Boot 17.4.8 Hardware and Software Constraints 17.5 SAM-BA Monitor 17.5.1 Command List 17.5.2 UART Port 17.5.2.1 Xmodem Protocol 17.5.3 USB Device Port 17.5.3.1 Supported External Crystal / External Clocks 17.5.3.2 USB Class 17.5.3.3 Enumeration Process 17.5.3.4 Communication Endpoints 17.6 Fuse Box Controller 17.6.1 Fuse Bit Mapping 18. AXI Matrix (AXIMX) 18.1 Description 18.2 Embedded Characteristics 18.3 Operation 18.3.1 Remap 18.4 AXI Matrix (AXIMX) User Interface 18.4.1 AXI Matrix Remap Register 19. Matrix (H64MX/H32MX) 19.1 Description 19.2 Embedded Characteristics 19.3 64-bit Matrix (H64MX) 19.3.1 Matrix Masters 19.3.2 Matrix Slaves 19.3.3 Master to Slave Access 19.4 32-bit Matrix (H32MX) 19.4.1 Matrix Masters 19.4.2 Matrix Slaves 19.4.3 Master to Slave Access 19.5 Memory Mapping 19.6 Special Bus Granting Mechanism 19.7 No Default Master 19.8 Last Access Master 19.9 Fixed Default Master 19.10 Arbitration 19.10.1 Arbitration Scheduling 19.10.1.1 Undefined Length Burst Arbitration 19.10.1.2 Slot Cycle Limit Arbitration 19.10.2 Arbitration Priority Scheme 19.10.2.1 Fixed Priority Arbitration 19.10.2.2 Round-robin Arbitration 19.11 Register Write Protection 19.12 TrustZone Extension to AHB and APB 19.12.1 Security Types of AHB Slaves 19.12.1.1 Principles 19.12.1.2 Examples 19.12.2 Security of APB Slaves 19.12.3 Security Types of AHB Master Peripherals 19.12.4 Security Types of AHB Slave Peripherals 19.13 Matrix (H64MX/H32MX) User Interface 19.13.1 Bus Matrix Master Configuration Registers 19.13.2 Bus Matrix Slave Configuration Registers 19.13.3 Bus Matrix Priority Registers A For Slaves 19.13.4 Bus Matrix Priority Registers B For Slaves 19.13.5 Master Error Interrupt Enable Register 19.13.6 Master Error Interrupt Disable Register 19.13.7 Master Error Interrupt Mask Register 19.13.8 Master Error Status Register 19.13.9 Master Error Address Registers 19.13.10 Write Protection Mode Register 19.13.11 Write Protection Status Register 19.13.12 Security Slave Registers 19.13.13 Security Areas Split Slave Registers 19.13.14 Security Region Top Slave Registers 19.13.15 Security Peripheral Select x Registers 20. Special Function Registers (SFR) 20.1 Description 20.2 Embedded Characteristics 20.3 Special Function Registers (SFR) User Interface 20.3.1 DDR Configuration Register 20.3.2 OHCI Interrupt Configuration Register 20.3.3 OHCI Interrupt Status Register 20.3.4 Security Configuration Register 20.3.5 UTMI Clock Trimming Register 20.3.6 UTMI High-Speed Trimming Register 20.3.7 UTMI Full-Speed Trimming Register 20.3.8 UMTI DP/DM Pin Swapping Register 20.3.9 CAN Memories Address-based Register 20.3.10 Serial Number 0 Register 20.3.11 Serial Number 1 Register 20.3.12 AIC Interrupt Redirection Register 20.3.13 HRAMC L2CC Register 20.3.14 I2S Register 20.3.15 QSPI Clock Pad Supply Select Register 21. Special Function Registers Backup (SFRBU) 21.1 Description 21.2 Embedded Characteristics 21.3 Special Function Registers Backup (SFRBU) User Interface 21.3.1 SFRBU Power Switch BU Control Register 21.3.2 SFRBU Temperature Sensor Range Configuration Register 21.3.3 SFRBU DDR BU Mode Control Register 21.3.4 SFRBU RXLP Pull-Up Control Register 22. Advanced Interrupt Controller (AIC) 22.1 Description 22.2 Embedded Characteristics 22.3 Block Diagram 22.4 Application Block Diagram 22.5 AIC Detailed Block Diagram 22.6 I/O Line Description 22.7 Product Dependencies 22.7.1 I/O Lines 22.7.2 Power Management 22.7.3 Interrupt Sources 22.8 Functional Description 22.8.1 Interrupt Source Control 22.8.1.1 Interrupt Source Mode 22.8.1.2 Interrupt Source Enabling 22.8.1.3 Interrupt Clearing and Setting 22.8.1.4 Interrupt Status 22.8.1.5 Internal Interrupt Source Input Stage 22.8.1.6 External Interrupt Source Input Stage 22.8.2 Interrupt Latencies 22.8.2.1 External Interrupt Edge Triggered Source 22.8.2.2 External Interrupt Level Sensitive Source 22.8.2.3 Internal Interrupt Edge Triggered Source 22.8.2.4 Internal Interrupt Level Sensitive Source 22.8.3 Normal Interrupt 22.8.3.1 Priority Controller 22.8.3.2 Interrupt Nesting 22.8.3.3 Interrupt Handlers 22.8.4 Fast Interrupt 22.8.4.1 Fast Interrupt Source 22.8.4.2 Fast Interrupt Control 22.8.4.3 Fast Interrupt Handlers 22.8.5 Protect Mode 22.8.6 Spurious Interrupt 22.8.7 General Interrupt Mask 22.8.8 Register Write Protection 22.9 Advanced Interrupt Controller (AIC) User Interface 22.9.1 AIC Source Select Register 22.9.2 AIC Source Mode Register 22.9.3 AIC Source Vector Register 22.9.4 AIC Interrupt Vector Register 22.9.5 AIC FIQ Vector Register 22.9.6 AIC Interrupt Status Register 22.9.7 AIC Interrupt Pending Register 0 22.9.8 AIC Interrupt Pending Register 1 22.9.9 AIC Interrupt Pending Register 2 22.9.10 AIC Interrupt Pending Register 3 22.9.11 AIC Interrupt Mask Register 22.9.12 AIC Core Interrupt Status Register 22.9.13 AIC End of Interrupt Command Register 22.9.14 AIC Spurious Interrupt Vector Register 22.9.15 AIC Interrupt Enable Command Register 22.9.16 AIC Interrupt Disable Command Register 22.9.17 AIC Interrupt Clear Command Register 22.9.18 AIC Interrupt Set Command Register 22.9.19 AIC Debug Control Register 22.9.20 AIC Write Protection Mode Register 22.9.21 AIC Write Protection Status Register 23. Watchdog Timer (WDT) 23.1 Description 23.2 Embedded Characteristics 23.3 Block Diagram 23.4 Functional Description 23.5 Watchdog Timer (WDT) User Interface 23.5.1 Watchdog Timer Control Register 23.5.2 Watchdog Timer Mode Register 23.5.3 Watchdog Timer Status Register 24. Reset Controller (RSTC) 24.1 Description 24.2 Embedded Characteristics 24.3 Block Diagram 24.4 Functional Description 24.4.1 Reset Controller Overview 24.4.2 NRST Manager 24.4.2.1 NRST Signal or Interrupt 24.4.3 Reset States 24.4.3.1 General Reset 24.4.3.2 Wakeup Reset 24.4.3.3 User Reset 24.4.3.4 Software Reset 24.4.3.5 Watchdog Reset 24.4.4 Reset State Priorities 24.5 Reset Controller (RSTC) User Interface 24.5.1 RSTC Control Register 24.5.2 RSTC Status Register 24.5.3 RSTC Mode Register 25. Shutdown Controller (SHDWC) 25.1 Description 25.2 Embedded Characteristics 25.3 Block Diagram 25.4 I/O Lines Description 25.5 Product Dependencies 25.5.1 Power Management 25.6 Functional Description 25.6.1 Wakeup Inputs 25.7 Shutdown Controller (SHDWC) User Interface 25.7.1 Shutdown Control Register 25.7.2 Shutdown Mode Register 25.7.3 Shutdown Status Register 25.7.4 Shutdown Wakeup Inputs Register 26. Periodic Interval Timer (PIT) 26.1 Description 26.2 Embedded Characteristics 26.3 Block Diagram 26.4 Functional Description 26.5 Periodic Interval Timer (PIT) User Interface 26.5.1 PIT Mode Register 26.5.2 PIT Status Register 26.5.3 PIT Value Register 26.5.4 PIT Image Register 27. Real-time Clock (RTC) 27.1 Description 27.2 Embedded Characteristics 27.3 Block Diagram 27.4 Product Dependencies 27.4.1 Power Management 27.4.2 Interrupt 27.5 Functional Description 27.5.1 Reference Clock 27.5.2 Timing 27.5.3 Alarm 27.5.4 Error Checking when Programming 27.5.5 RTC Internal Free Running Counter Error Checking 27.5.6 Updating Time/Calendar 27.5.6.1 Gregorian and Persian Modes 27.5.6.2 UTC Mode 27.5.7 RTC Accurate Clock Calibration 27.5.8 Waveform Generation 27.5.9 Tamper Timestamping 27.6 Real-time Clock (RTC) User Interface 27.6.1 RTC Control Register 27.6.2 RTC Mode Register 27.6.3 RTC Time Register 27.6.4 RTC Time Register (UTC_MODE) 27.6.5 RTC Calendar Register 27.6.6 RTC Time Alarm Register 27.6.7 RTC Time Alarm Register (UTC_MODE) 27.6.8 RTC Calendar Alarm Register 27.6.9 RTC Calendar Alarm Register (UTC_MODE) 27.6.10 RTC Status Register 27.6.11 RTC Status Clear Command Register 27.6.12 RTC Interrupt Enable Register 27.6.13 RTC Interrupt Disable Register 27.6.14 RTC Interrupt Mask Register 27.6.15 RTC Valid Entry Register 27.6.16 RTC TimeStamp Time Register 0 27.6.17 RTC TimeStamp Time Register 0 (UTC_MODE) 27.6.18 RTC TimeStamp Time Register 1 27.6.19 RTC TimeStamp Time Register 1 (UTC_MODE) 27.6.20 RTC TimeStamp Date Register 27.6.21 RTC TimeStamp Date Register (UTC_MODE) 27.6.22 RTC TimeStamp Source Register 28. System Controller Write Protection (SYSCWP) 28.1 Functional Description 28.2 System Controller Write Protect (SYSCWP) User Interface 28.2.1 System Controller Write Protection Mode Register 29. Slow Clock Controller (SCKC) 29.1 Description 29.2 Embedded Characteristics 29.3 Block Diagram 29.4 Functional Description 29.4.1 Switching from Embedded 64 kHz RC Oscillator to 32.768 kHz Crystal Oscillator 29.4.2 Switching from 32.768 kHz Crystal Oscillator to Embedded 64 kHz RC Oscillator 29.5 Slow Clock Controller (SCKC) User Interface 29.5.1 Slow Clock Controller Configuration Register 30. Peripheral Touch Controller (PTC) 30.1 Description 30.2 Embedded Characteristics 30.3 Block Diagram 30.4 Signal Description 30.5 Product Dependencies 30.5.1 Power Management 30.5.2 I/O Lines 30.5.3 Interrupt Sources 30.6 Functional Description 30.6.1 picoPower Processor (pPP) 30.6.2 Shared Memories 30.6.2.1 Mailbox 30.6.2.2 SRAM Data Area 30.6.2.3 Firmware in SRAM Code Area 30.6.2.4 Host Interface 30.6.3 PTC Digital Controller 30.6.3.1 PTC Digital Controller Operations 30.6.4 PTC Analog Front End (AFE) 30.6.5 Operations in Mutual Capacitance 30.6.6 Operations in Self-capacitance 30.7 Peripheral Touch Controller (PTC) User Interface 30.7.1 PTC Command Register 30.7.2 PTC Interrupt Status Register 30.7.3 PTC Enable Register 31. Low Power Asynchronous Receiver (RXLP) 31.1 Description 31.2 Embedded Characteristics 31.3 Block Diagram 31.4 Product Dependencies 31.4.1 Power Management 31.5 Functional Description 31.5.1 Baud Rate Generator 31.5.2 Receiver 31.5.2.1 Receiver Reset, Enable and Disable 31.5.2.2 Start Detection and Data Sampling 31.5.2.3 Parity Error 31.5.2.4 Receiver Framing Error 31.5.2.5 Receiver Digital Filter 31.5.3 Comparison Function on Received Character 31.5.4 Register Write Protection 31.6 Low Power Asynchronous Receiver (RXLP) User Interface 31.6.1 RXLP Control Register 31.6.2 RXLP Mode Register 31.6.3 RXLP Receiver Holding Register 31.6.4 RXLP Baud Rate Generator Register 31.6.5 RXLP Comparison Register 31.6.6 RXLP Write Protection Mode Register 32. Analog Comparator Controller (ACC) 32.1 Description 32.2 Embedded Characteristics 32.3 Block Diagram 32.4 Signal Description 32.5 Product Dependencies 32.5.1 I/O Lines 32.5.2 Power Management 32.6 Functional Description 32.6.1 Description 32.6.2 Register Write Protection 32.7 Analog Comparator Controller (ACC) User Interface 32.7.1 ACC Control Register 32.7.2 ACC Mode Register 32.7.3 ACC Write Protection Mode Register 32.7.4 ACC Write Protection Status Register 33. Clock Generator 33.1 Description 33.2 Embedded Characteristics 33.3 Block Diagram 33.4 Slow Clock 33.4.1 Embedded 64 kHz (typical) RC Oscillator 33.4.2 32.768 kHz Crystal Oscillator 33.5 Main Clock 33.5.1 12 MHz RC Oscillator 33.5.2 12 MHz RC Oscillator Clock Frequency Adjustment 33.5.3 8 to 24 MHz Crystal Oscillator 33.5.4 Main Clock Source Selection 33.5.5 Bypassing the 8 to 24 MHz Crystal Oscillator 33.5.6 Main Frequency Counter 33.5.7 Switching Main Clock Between the RC Oscillator and the Crystal Oscillator 33.6 Divider and PLLA Block 33.6.1 Divider and Phase Lock Loop Programming 33.7 UTMI PLL Clock 33.8 Audio PLL 34. Power Management Controller (PMC) 34.1 Description 34.2 Embedded Characteristics 34.3 Block Diagram 34.4 Master Clock Controller 34.5 Processor Clock Controller 34.6 Matrix Clock Controller 34.7 Programmable Clock Controller 34.8 Core and Bus Independent Clocks for Peripherals 34.9 Peripheral and Generic Clock Controller 34.10 LCDC Clock Controller 34.11 ISC Clock Controller 34.12 USB Device and Host Clocks 34.13 DDR2/LPDDR/LPDDR2 Clock Controller 34.14 Fast Startup from Ultra Low-power (ULP) Mode 0 34.15 Fast Startup from Ultra Low-Power (ULP) Mode 1 34.16 Asynchronous Partial Wakeup (SleepWalking) 34.16.1 Description 34.16.2 Configuration Procedure 34.17 Main Crystal Oscillator Failure Detection 34.18 32.768 kHz Crystal Oscillator Frequency Monitor 34.19 Programming Sequence 34.20 Clock Switching Details 34.20.1 Master Clock Switching Timings 34.20.2 Clock Switching Waveforms 34.21 Register Write Protection 34.22 Power Management Controller (PMC) User Interface 34.22.1 PMC System Clock Enable Register 34.22.2 PMC System Clock Disable Register 34.22.3 PMC System Clock Status Register 34.22.4 PMC Peripheral Clock Enable Register 0 34.22.5 PMC Peripheral Clock Disable Register 0 34.22.6 PMC Peripheral Clock Status Register 0 34.22.7 PMC UTMI Clock Configuration Register 34.22.8 PMC Clock Generator Main Oscillator Register 34.22.9 PMC Clock Generator Main Clock Frequency Register 34.22.10 PMC Clock Generator PLLA Register 34.22.11 PMC Master Clock Register 34.22.12 PMC USB Clock Register 34.22.13 PMC Programmable Clock Register 34.22.14 PMC Interrupt Enable Register 34.22.15 PMC Interrupt Disable Register 34.22.16 PMC Status Register 34.22.17 PMC Interrupt Mask Register 34.22.18 PMC Fast Startup Polarity Register 34.22.19 PMC Fast Startup Mode Register 34.22.20 PMC Fault Output Clear Register 34.22.21 PLL Charge Pump Current Register 34.22.22 PMC Write Protection Mode Register 34.22.23 PMC Write Protection Status Register 34.22.24 PMC Peripheral Clock Enable Register 1 34.22.25 PMC Peripheral Clock Disable Register 1 34.22.26 PMC Peripheral Clock Status Register 1 34.22.27 PMC Peripheral Control Register 34.22.28 PMC Oscillator Calibration Register 34.22.29 PMC SleepWalking Enable Register 0 34.22.30 PMC SleepWalking Disable Register 0 34.22.31 PMC SleepWalking Status Register 0 34.22.32 PMC SleepWalking Activity Status Register 0 34.22.33 PMC SleepWalking Enable Register 1 34.22.34 PMC SleepWalking Disable Register 1 34.22.35 PMC SleepWalking Status Register 1 34.22.36 PMC SleepWalking Activity Status Register 1 34.22.37 PMC SleepWalking Activity In Progress Register 34.22.38 PMC SleepWalking Control Register 34.22.39 PMC Audio PLL Control Register 0 34.22.40 PMC Audio PLL Control Register 1 35. Parallel Input/Output Controller (PIO) 35.1 Description 35.2 Embedded Characteristics 35.3 Block Diagram 35.4 Product Dependencies 35.4.1 Pin Multiplexing 35.4.2 External Interrupt Lines 35.4.3 Power Management 35.4.4 Interrupt Generation 35.5 Functional Description 35.5.1 I/O Line Configuration Method 35.5.1.1 Security Management 35.5.1.2 Programming I/O Line Configuration 35.5.1.3 Reading I/O line configuration 35.5.2 Pull-up and Pull-down Resistor Control 35.5.3 General Purpose or Peripheral Function Selection 35.5.4 Output Control 35.5.5 Synchronous Data Output 35.5.6 Open-Drain Mode 35.5.7 Output Line Timings 35.5.8 Inputs 35.5.9 Input Glitch and Debouncing Filters 35.5.10 Input Edge/Level Interrupt 35.5.11 Interrupt Management 35.5.12 I/O Lines Lock 35.5.13 Programmable I/O Drive 35.5.14 Programmable Schmitt Trigger 35.5.15 I/O Line Configuration Freeze 35.5.15.1 Software Freeze 35.5.16 Register Write Protection 35.6 I/O Lines Programming Example 35.7 Parallel Input/Output Controller (PIO) User Interface 35.7.1 PIO Mask Register 35.7.2 PIO Configuration Register 35.7.3 PIO Pin Data Status Register 35.7.4 PIO Lock Status Register 35.7.5 PIO Set Output Data Register 35.7.6 PIO Clear Output Data Register 35.7.7 PIO Output Data Status Register 35.7.8 PIO Interrupt Enable Register 35.7.9 PIO Interrupt Disable Register 35.7.10 PIO Interrupt Mask Register 35.7.11 PIO Interrupt Status Register 35.7.12 PIO I/O Freeze Configuration Register 35.7.13 PIO Write Protection Mode Register 35.7.14 PIO Write Protection Status Register 35.7.15 Secure PIO Mask Register 35.7.16 Secure PIO Configuration Register 35.7.17 Secure PIO Pin Data Status Register 35.7.18 Secure PIO Lock Status Register 35.7.19 Secure PIO Set Output Data Register 35.7.20 Secure PIO Clear Output Data Register 35.7.21 Secure PIO Output Data Status Register 35.7.22 Secure PIO Interrupt Enable Register 35.7.23 Secure PIO Interrupt Disable Register 35.7.24 Secure PIO Interrupt Mask Register 35.7.25 Secure PIO Interrupt Status Register 35.7.26 Secure PIO Set I/O Non-Secure Register 35.7.27 Secure PIO Set I/O Secure Register 35.7.28 Secure PIO I/O Security Status Register 35.7.29 Secure PIO I/O Freeze Configuration Register 35.7.30 Secure PIO Slow Clock Divider Debouncing Register 35.7.31 Secure PIO Write Protection Mode Register 35.7.32 Secure PIO Write Protection Status Register 36. External Memories 36.1 Multiport DDR-SDRAM Controller (MPDDRC) 36.1.1 Description 36.1.2 MPDDR Controller Block Diagram 36.1.3 I/O Lines Description 36.1.4 Product Dependencies 36.1.5 Implementation Example 36.1.5.1 16-bit DDR2 36.1.5.2 2x16-bit DDR2 36.1.5.3 16-bit DDR3/DDR3L 36.1.5.4 2x16-bit DDR3/DDR3L 36.1.5.5 2x16-bit LPDDR2/LPDDR3 36.2 External Bus Interface (EBI) 36.2.1 Description 36.2.2 Implementation Examples 36.2.2.1 8-bit NAND Flash 36.2.2.2 16-bit NAND Flash 36.2.2.3 NOR Flash on NCS0 37. Multiport DDR-SDRAM Controller (MPDDRC) 37.1 Description 37.2 Embedded Characteristics 37.3 MPDDRC Module Diagram 37.4 Product Dependencies, Initialization Sequence 37.4.1 Low-power DDR1-SDRAM Initialization 37.4.2 DDR2-SDRAM Initialization 37.4.3 Low-power DDR2-SDRAM Initialization 37.4.4 DDR3-SDRAM/DDR3L-SDRAM Initialization 37.4.5 Low-power DDR3-SDRAM Initialization 37.5 Functional Description 37.5.1 DDR-SDRAM Controller Write Cycle 37.5.2 DDR-SDRAM Controller Read Cycle 37.5.2.1 All Banks Autorefresh 37.5.2.2 Per-bank Autorefresh 37.5.2.3 Adjust Autorefresh Rate 37.5.3 Power Management 37.5.3.1 Self-refresh Mode 37.5.3.2 Powerdown Mode 37.5.3.3 Deep Powerdown Mode 37.5.3.4 Change Frequency During Self-Refresh Mode with Low-power DDR-SDRAM Devices and DDR3-SDRAM 37.5.3.5 Reset Mode 37.5.4 Multiport Functionality 37.5.4.1 Round-robin Arbitration 37.5.4.2 Request-word Weighted Round-robin Arbitration 37.5.4.3 Bandwidth Weighted Round-robin Arbitration 37.5.5 Scrambling/Unscrambling Function 37.5.6 Register Write Protection 37.6 Software Interface/SDRAM Organization, Address Mapping 37.6.1 DDR-SDRAM Address Mapping for 16-bit Memory Data Bus Width 37.6.2 DDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width 37.6.3 DDR-SDRAM Address Mapping for Low-cost Memories 37.7 AHB Multiport DDR-SDRAM Controller (MPDDRC) User Interface 37.7.1 MPDDRC Mode Register 37.7.2 MPDDRC Refresh Timer Register 37.7.3 MPDDRC Configuration Register 37.7.4 MPDDRC Timing Parameter 0 Register 37.7.5 MPDDRC Timing Parameter 1 Register 37.7.6 MPDDRC Timing Parameter 2 Register 37.7.7 MPDDRC Low-Power Register 37.7.8 MPDDRC Memory Device Register 37.7.9 MPDDRC Low-power DDR2 Low-power DDR3 Low-power Register 37.7.10 MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Calibration and MR4 Register 37.7.11 MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register 37.7.12 MPDDRC I/O Calibration Register 37.7.13 MPDDRC OCMS Register 37.7.14 MPDDRC OCMS KEY1 Register 37.7.15 MPDDRC OCMS KEY2 Register 37.7.16 MPDDRC Configuration Arbiter Register 37.7.17 MPDDRC Timeout Register 37.7.18 MPDDRC Request Port 0-1-2-3 Register 37.7.19 MPDDRC Request Port 4-5-6-7 Register 37.7.20 MPDDRC Current/Maximum Bandwidth Port 0-1-2-3 Register 37.7.21 MPDDRC Current/Maximum Bandwidth Port 4-5-6-7 Register 37.7.22 MPDDRC Read Data Path Register 37.7.23 MPDDRC Monitor Configuration Register 37.7.24 MPDDRC Monitor Address High/Low Port x Register 37.7.25 MPDDRC Monitor Information Port x Register (MAX_WAIT) 37.7.26 MPDDRC Monitor Information Port x Register (NB_TRANSFERS) 37.7.27 MPDDRC Monitor Information Port x Register (TOTAL_LATENCY) 37.7.28 MPDDRC Write Protection Mode Register 37.7.29 MPDDRC Write Protection Status Register 38. Static Memory Controller (SMC) 38.1 Description 38.2 Embedded Characteristics 38.3 Block Diagram 38.4 I/O Lines Description 38.5 Multiplexed Signals 38.6 Application Example 38.6.1 Hardware Interface 38.7 Product Dependencies 38.7.1 I/O Lines 38.7.2 Power Management 38.7.3 Interrupt Sources 38.8 External Memory Mapping 38.9 Connection to External Devices 38.9.1 Data Bus Width 38.9.2 Byte Write or Byte Select Access 38.9.2.1 Byte Write Access 38.9.2.2 Byte Select Access 38.9.2.3 Signal Multiplexing 38.10 Standard Read and Write Protocols 38.10.1 Read Waveforms 38.10.1.1 NRD Waveform 38.10.1.2 NCS Waveform 38.10.1.3 Read Cycle 38.10.2 Read Mode 38.10.2.1 Read is Controlled by NRD (READ_MODE = 1) 38.10.2.2 Read is Controlled by NCS (READ_MODE = 0) 38.10.3 Write Waveforms 38.10.3.1 NWE Waveforms 38.10.3.2 NCS Waveforms 38.10.3.3 Write Cycle 38.10.4 Write Mode 38.10.4.1 Write is Controlled by NWE (WRITE_MODE = 1) 38.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0) 38.10.5 Coding Timing Parameters 38.10.6 Reset Values of Timing Parameters 38.10.7 Usage Restriction 38.10.7.1 For Read Operations 38.10.7.2 For Write Operations 38.10.7.3 For Read and Write Operations 38.11 Scrambling/Unscrambling Function 38.12 Automatic Wait States 38.12.1 Chip Select Wait States 38.12.2 Early Read Wait State 38.12.3 Reload User Configuration Wait State 38.12.3.1 User Procedure 38.12.3.2 Slow Clock Mode Transition 38.12.4 Read to Write Wait State 38.13 Data Float Wait States 38.13.1 READ_MODE 38.13.2 TDF Optimization Enabled (TDF_MODE = 1) 38.13.3 TDF Optimization Disabled (TDF_MODE = 0) 38.14 External Wait 38.14.1 Restriction 38.14.2 Frozen Mode 38.14.3 Ready Mode 38.14.4 NWAIT Latency and Read/Write Timings 38.15 Slow Clock Mode 38.15.1 Slow Clock Mode Waveforms 38.15.2 Switching from (to) Slow Clock Mode to (from) Normal Mode 38.16 Register Write Protection 38.17 NFC Operations 38.17.1 NFC Overview 38.17.2 NFC Control Registers 38.17.2.1 Building NFC Address Command Example 38.17.2.2 NFC Address Command 38.17.2.3 NFC Data Address 38.17.2.4 NFC DATA Status 38.17.3 NFC Initialization 38.17.3.1 NFC Timing Engine 38.17.4 NFC SRAM 38.17.4.1 NFC SRAM Mapping 38.17.4.2 NFC SRAM Access Prioritization Algorithm 38.17.5 NAND Flash Operations 38.17.5.1 Page Read 38.17.5.2 Program Page 38.18 PMECC Controller Functional Description 38.18.1 MLC/SLC Write Page Operation Using PMECC 38.18.1.1 SLC/MLC Write Operation with Spare Enable Bit Set 38.18.1.2 SLC/MLC Write Operation with Spare Disable 38.18.2 MLC/SLC Read Page Operation Using PMECC 38.18.2.1 MLC/SLC Read Operation with Spare Decoding 38.18.2.2 MLC/SLC Read Operation 38.18.2.3 MLC/SLC User Read ECC Area 38.18.2.4 MLC Controller Working with NFC 38.19 Software Implementation 38.19.1 Remainder Substitution Procedure 38.19.2 Finding the Error Location Polynomial Sigma(x) 38.19.3 Finding the Error Position 38.19.3.1 Error Location 38.20 Static Memory Controller (SMC) User Interface 38.20.1 NFC Configuration Register 38.20.2 NFC Control Register 38.20.3 NFC Status Register 38.20.4 NFC Interrupt Enable Register 38.20.5 NFC Interrupt Disable Register 38.20.6 NFC Interrupt Mask Register 38.20.7 NFC Address Cycle Zero Register 38.20.8 NFC Bank Register 38.20.9 PMECC Configuration Register 38.20.10 PMECC Spare Area Size Register 38.20.11 PMECC Start Address Register 38.20.12 PMECC End Address Register 38.20.13 PMECC Control Register 38.20.14 PMECC Status Register 38.20.15 PMECC Interrupt Enable Register 38.20.16 PMECC Interrupt Disable Register 38.20.17 PMECC Interrupt Mask Register 38.20.18 PMECC Interrupt Status Register 38.20.19 PMECC Redundancy x Register 38.20.20 PMECC Remainder x Register 38.20.21 PMECC Error Location Configuration Register 38.20.22 PMECC Error Location Primitive Register 38.20.23 PMECC Error Location Enable Register 38.20.24 PMECC Error Location Disable Register 38.20.25 PMECC Error Location Status Register 38.20.26 PMECC Error Location Interrupt Enable Register 38.20.27 PMECC Error Location Interrupt Disable Register 38.20.28 PMECC Error Location Interrupt Mask Register 38.20.29 PMECC Error Location Interrupt Status Register 38.20.30 PMECC Error Location SIGMA0 Register 38.20.31 PMECC Error Location SIGMAx Register 38.20.32 PMECC Error Location x Register 38.20.33 Setup Register 38.20.34 Pulse Register 38.20.35 Cycle Register 38.20.36 Timings Register 38.20.37 Mode Register 38.20.38 Off Chip Memory Scrambling Register 38.20.39 Off Chip Memory Scrambling Key1 Register 38.20.40 Off Chip Memory Scrambling Key2 Register 38.20.41 Write Protection Mode Register 38.20.42 Write Protection Status Register 39. DMA Controller (XDMAC) 39.1 Description 39.2 Embedded Characteristics 39.3 Block Diagram 39.4 DMA Controller Peripheral Connections 39.5 Functional Description 39.5.1 Basic Definitions 39.5.2 Transfer Hierarchy Diagram 39.5.3 Peripheral Synchronized Transfer 39.5.3.1 Software Triggered Synchronized Transfer 39.5.4 XDMAC Transfer Software Operation 39.5.4.1 Single Block With Single Microblock Transfer 39.5.4.2 Single Block Transfer With Multiple Microblock 39.5.4.3 Master Transfer 39.5.4.4 Disabling A Channel Before Transfer Completion 39.6 Linked List Descriptor Operation 39.6.1 Linked List Descriptor View 39.6.1.1 Channel Next Descriptor View 0–3 Structures 39.6.2 Descriptor Structure Members Description 39.6.2.1 Descriptor Structure Microblock Control Member 39.7 XDMAC Maintenance Software Operations 39.7.1 Disabling a Channel 39.7.2 Suspending a Channel 39.7.3 Flushing a Channel 39.7.4 Maintenance Operation Priority 39.7.4.1 Disable Operation Priority 39.7.4.2 Flush Operation Priority 39.7.4.3 Suspend Operation Priority 39.8 XDMAC Software Requirements 39.9 Extensible DMA Controller (XDMAC) User Interface 39.9.1 XDMAC Global Type Register 39.9.2 XDMAC Global Configuration Register 39.9.3 XDMAC Global Weighted Arbiter Configuration Register 39.9.4 XDMAC Global Interrupt Enable Register 39.9.5 XDMAC Global Interrupt Disable Register 39.9.6 XDMAC Global Interrupt Mask Register 39.9.7 XDMAC Global Interrupt Status Register 39.9.8 XDMAC Global Channel Enable Register 39.9.9 XDMAC Global Channel Disable Register 39.9.10 XDMAC Global Channel Status Register 39.9.11 XDMAC Global Channel Read Suspend Register 39.9.12 XDMAC Global Channel Write Suspend Register 39.9.13 XDMAC Global Channel Read Write Suspend Register 39.9.14 XDMAC Global Channel Read Write Resume Register 39.9.15 XDMAC Global Channel Software Request Register 39.9.16 XDMAC Global Channel Software Request Status Register 39.9.17 XDMAC Global Channel Software Flush Request Register 39.9.18 XDMAC Channel x [x = 0..15] Interrupt Enable Register 39.9.19 XDMAC Channel x [x = 0..15] Interrupt Disable Register 39.9.20 XDMAC Channel x [x = 0..15] Interrupt Mask Register 39.9.21 XDMAC Channel x [x = 0..15] Interrupt Status Register 39.9.22 XDMAC Channel x [x = 0..15] Source Address Register 39.9.23 XDMAC Channel x [x = 0..15] Destination Address Register 39.9.24 XDMAC Channel x [x = 0..15] Next Descriptor Address Register 39.9.25 XDMAC Channel x [x = 0..15] Next Descriptor Control Register 39.9.26 XDMAC Channel x [x = 0..15] Microblock Control Register 39.9.27 XDMAC Channel x [x = 0..15] Block Control Register 39.9.28 XDMAC Channel x [x = 0..15] Configuration Register 39.9.29 XDMAC Channel x [x = 0..15] Data Stride Memory Set Pattern Register 39.9.30 XDMAC Channel x [x = 0..15] Source Microblock Stride Register 39.9.31 XDMAC Channel x [x = 0..15] Destination Microblock Stride Register 40. LCD Controller (LCDC) 40.1 Description 40.2 Embedded Characteristics 40.3 Block Diagram 40.4 I/O Lines Description 40.5 Product Dependencies 40.5.1 I/O Lines 40.5.2 Power Management 40.5.3 Interrupt Sources 40.6 Functional Description 40.6.1 Timing Engine Configuration 40.6.1.1 Pixel Clock Period Configuration 40.6.1.2 Horizontal and Vertical Synchronization Configuration 40.6.1.3 Timing Engine Powerup Software Operation 40.6.1.4 Timing Engine Powerdown Software Operation 40.6.2 DMA Software Operations 40.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure 40.6.2.2 Enabling a DMA Channel 40.6.2.3 Disabling a DMA Channel 40.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor 40.6.2.5 DMA Interrupt Generation 40.6.2.6 DMA Address Alignment Requirements 40.6.3 Overlay Software Configuration 40.6.3.1 System Bus Access Attributes 40.6.3.2 Color Attributes 40.6.3.3 Window Position, Size, Scaling and Striding Attributes 40.6.3.4 Overlay Blender Attributes 40.6.3.5 Overlay Attributes Software Operation 40.6.4 RGB Frame Buffer Memory Bitmap 40.6.4.1 1 bpp Through Color Lookup Table 40.6.4.2 2 bpp Through Color Lookup Table 40.6.4.3 4 bpp Through Color Lookup Table 40.6.4.4 8 bpp Through Color Lookup Table 40.6.4.5 12 bpp Memory Mapping, RGB 4:4:4 40.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 40.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 40.6.4.8 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5 40.6.4.9 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5 40.6.4.10 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6 40.6.4.11 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 40.6.4.12 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6 40.6.4.13 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6 40.6.4.14 24 bpp Unpacked Memory Mapping, RGB 8:8:8 40.6.4.15 24 bpp Packed Memory Mapping, RGB 8:8:8 40.6.4.16 25 bpp Memory Mapping, ARGB 1:8:8:8 40.6.4.17 32 bpp Memory Mapping, ARGB 8:8:8:8 40.6.4.18 32 bpp Memory Mapping, RGBA 8:8:8:8 40.6.5 YUV Frame Buffer Memory Mapping 40.6.5.1 AYCbCr 4:4:4 Interleaved Frame Buffer Memory Mapping 40.6.5.2 4:2:2 Interleaved Mode Frame Buffer Memory Mapping 40.6.5.3 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping 40.6.5.4 4:2:2 Planar Mode Frame Buffer Memory Mapping 40.6.5.5 4:2:0 Planar Mode Frame Buffer Memory Mapping 40.6.5.6 4:2:0 Semiplanar Frame Buffer Memory Mapping 40.6.6 Chrominance Upsampling Unit 40.6.6.1 Chrominance Upsampling Algorithm 40.6.7 Line and Pixel Striding 40.6.7.1 Line Striding 40.6.7.2 Pixel Striding 40.6.8 Color Space Conversion Unit 40.6.9 Two-Dimension Scaler 40.6.9.1 Video Scaler Description 40.6.9.2 Horizontal Scaler 40.6.9.3 Vertical Scaler 40.6.10 Color Combine Unit 40.6.10.1 Window Overlay 40.6.10.2 Base Layer with Window Overlay Optimization 40.6.10.3 Overlay Blending 40.6.10.4 Window Blending 40.6.10.5 Color Keying 40.6.11 LCDC PWM Controller 40.6.12 Post Processing Controller 40.6.13 LCD Overall Performance 40.6.13.1 Color Lookup Table (CLUT) 40.6.13.2 RGB Mode Fetch Performance 40.6.13.3 YUV Mode Fetch Performance 40.6.14 Input FIFO 40.6.15 Output FIFO 40.6.16 Output Timing Generation 40.6.16.1 Active Display Timing Mode 40.6.17 Output Format 40.6.17.1 Active Mode Output Pin Assignment 40.7 LCD Controller (LCDC) User Interface 40.7.1 LCD Controller Configuration Register 0 40.7.2 LCD Controller Configuration Register 1 40.7.3 LCD Controller Configuration Register 2 40.7.4 LCD Controller Configuration Register 3 40.7.5 LCD Controller Configuration Register 4 40.7.6 LCD Controller Configuration Register 5 40.7.7 LCD Controller Configuration Register 6 40.7.8 LCD Controller Enable Register 40.7.9 LCD Controller Disable Register 40.7.10 LCD Controller Status Register 40.7.11 LCD Controller Interrupt Enable Register 40.7.12 LCD Controller Interrupt Disable Register 40.7.13 LCD Controller Interrupt Mask Register 40.7.14 LCD Controller Interrupt Status Register 40.7.15 LCD Controller Attribute Register 40.7.16 Base Layer Channel Enable Register 40.7.17 Base Layer Channel Disable Register 40.7.18 Base Layer Channel Status Register 40.7.19 Base Layer Interrupt Enable Register 40.7.20 Base Layer Interrupt Disable Register 40.7.21 Base Layer Interrupt Mask Register 40.7.22 Base Layer Interrupt Status Register 40.7.23 Base DMA Head Register 40.7.24 Base DMA Address Register 40.7.25 Base DMA Control Register 40.7.26 Base DMA Next Register 40.7.27 Base Layer Configuration Register 0 40.7.28 Base Layer Configuration Register 1 40.7.29 Base Layer Configuration Register 2 40.7.30 Base Layer Configuration Register 3 40.7.31 Base Layer Configuration Register 4 40.7.32 Base Layer Configuration Register 5 40.7.33 Base Layer Configuration Register 6 40.7.34 Overlay 1 Channel Enable Register 40.7.35 Overlay 1 Channel Disable Register 40.7.36 Overlay 1 Channel Status Register 40.7.37 Overlay 1 Interrupt Enable Register 40.7.38 Overlay 1 Interrupt Disable Register 40.7.39 Overlay 1 Interrupt Mask Register 40.7.40 Overlay 1 Interrupt Status Register 40.7.41 Overlay 1 Head Register 40.7.42 Overlay 1 Address Register 40.7.43 Overlay 1 Control Register 40.7.44 Overlay 1 Next Register 40.7.45 Overlay 1 Configuration Register 0 40.7.46 Overlay 1 Configuration Register 1 40.7.47 Overlay 1 Configuration Register 2 40.7.48 Overlay 1 Configuration Register 3 40.7.49 Overlay 1 Configuration Register 4 40.7.50 Overlay 1 Configuration Register 5 40.7.51 Overlay 1 Configuration Register 6 40.7.52 Overlay 1 Configuration Register 7 40.7.53 Overlay 1 Configuration Register 8 40.7.54 Overlay 1 Configuration Register 9 40.7.55 Overlay 2 Channel Enable Register 40.7.56 Overlay 2 Channel Disable Register 40.7.57 Overlay 2 Channel Status Register 40.7.58 Overlay 2 Interrupt Enable Register 40.7.59 Overlay 2 Interrupt Disable Register 40.7.60 Overlay 2 Interrupt Mask Register 40.7.61 Overlay 2 Interrupt Status Register 40.7.62 Overlay 2 Head Register 40.7.63 Overlay 2 Address Register 40.7.64 Overlay 2 Control Register 40.7.65 Overlay 2 Next Register 40.7.66 Overlay 2 Configuration Register 0 40.7.67 Overlay 2 Configuration Register 1 40.7.68 Overlay 2 Configuration Register 2 40.7.69 Overlay 2 Configuration Register 3 40.7.70 Overlay 2 Configuration Register 4 40.7.71 Overlay 2 Configuration Register 5 40.7.72 Overlay 2 Configuration Register 6 40.7.73 Overlay 2 Configuration Register 7 40.7.74 Overlay 2 Configuration Register 8 40.7.75 Overlay 2 Configuration Register 9 40.7.76 High-End Overlay Channel Enable Register 40.7.77 High-End Overlay Channel Disable Register 40.7.78 High-End Overlay Channel Status Register 40.7.79 High-End Overlay Interrupt Enable Register 40.7.80 High-End Overlay Interrupt Disable Register 40.7.81 High-End Overlay Interrupt Mask Register 40.7.82 High-End Overlay Interrupt Status Register 40.7.83 High-End Overlay DMA Head Register 40.7.84 High-End Overlay DMA Address Register 40.7.85 High-End Overlay DMA Control Register 40.7.86 High-End Overlay DMA Next Register 40.7.87 High-End Overlay U-UV DMA Head Register 40.7.88 High-End Overlay U-UV DMA Address Register 40.7.89 High-End Overlay U-UV DMA Control Register 40.7.90 High-End Overlay U-UV DMA Next Register 40.7.91 High-End Overlay V DMA Head Register 40.7.92 High-End Overlay V DMA Address Register 40.7.93 High-End Overlay V DMA Control Register 40.7.94 High-End Overlay V DMA Next Register 40.7.95 High-End Overlay Configuration Register 0 40.7.96 High-End Overlay Configuration Register 1 40.7.97 High-End Overlay Configuration Register 2 40.7.98 High-End Overlay Configuration Register 3 40.7.99 High-End Overlay Configuration Register 4 40.7.100 High-End Overlay Configuration Register 5 40.7.101 High-End Overlay Configuration Register 6 40.7.102 High-End Overlay Configuration Register 7 40.7.103 High-End Overlay Configuration Register 8 40.7.104 High-End Overlay Configuration Register 9 40.7.105 High-End Overlay Configuration Register 10 40.7.106 High-End Overlay Configuration Register 11 40.7.107 High-End Overlay Configuration Register 12 40.7.108 High-End Overlay Configuration Register 13 40.7.109 High-End Overlay Configuration Register 14 40.7.110 High-End Overlay Configuration Register 15 40.7.111 High-End Overlay Configuration Register 16 40.7.112 High-End Overlay Configuration Register 17 40.7.113 High-End Overlay Configuration Register 18 40.7.114 High-End Overlay Configuration Register 19 40.7.115 High-End Overlay Configuration Register 20 40.7.116 High-End Overlay Configuration Register 21 40.7.117 High-End Overlay Configuration Register 22 40.7.118 High-End Overlay Configuration Register 23 40.7.119 High-End Overlay Configuration Register 24 40.7.120 High-End Overlay Configuration Register 25 40.7.121 High-End Overlay Configuration Register 26 40.7.122 High-End Overlay Configuration Register 27 40.7.123 High-End Overlay Configuration Register 28 40.7.124 High-End Overlay Configuration Register 29 40.7.125 High-End Overlay Configuration Register 30 40.7.126 High-End Overlay Configuration Register 31 40.7.127 High-End Overlay Configuration Register 32 40.7.128 High-End Overlay Configuration Register 33 40.7.129 High-End Overlay Configuration Register 34 40.7.130 High-End Overlay Configuration Register 35 40.7.131 High-End Overlay Configuration Register 36 40.7.132 High-End Overlay Configuration Register 37 40.7.133 High-End Overlay Configuration Register 38 40.7.134 High-End Overlay Configuration Register 39 40.7.135 High-End Overlay Configuration Register 40 40.7.136 High-End Overlay Configuration Register 41 40.7.137 Post Processing Channel Enable Register 40.7.138 Post Processing Channel Disable Register 40.7.139 Post Processing Channel Status Register 40.7.140 Post Processing Interrupt Enable Register 40.7.141 Post Processing Interrupt Disable Register 40.7.142 Post Processing Interrupt Mask Register 40.7.143 Post Processing Interrupt Status Register 40.7.144 Post Processing Head Register 40.7.145 Post Processing Address Register 40.7.146 Post Processing Control Register 40.7.147 Post Processing Next Register 40.7.148 Post Processing Configuration Register 0 40.7.149 Post Processing Configuration Register 1 40.7.150 Post Processing Configuration Register 2 40.7.151 Post Processing Configuration Register 3 40.7.152 Post Processing Configuration Register 4 40.7.153 Post Processing Configuration Register 5 40.7.154 Base CLUT Register x 40.7.155 Overlay 1 CLUT Register x 40.7.156 Overlay 2 CLUT Register x 40.7.157 High-End Overlay CLUT Register x 41. Ethernet MAC (GMAC) 41.1 Description 41.2 Embedded Characteristics 41.3 Block Diagram 41.4 Signal Interfaces 41.5 Product Dependencies 41.5.1 I/O Lines 41.5.2 Power Management 41.5.3 Interrupt Sources 41.6 Functional Description 41.6.1 Media Access Controller 41.6.2 1588 Timestamp Unit 41.6.3 AHB Direct Memory Access Interface 41.6.3.1 Packet Buffer DMA 41.6.3.2 Partial Store and Forward Using Packet Buffer DMA 41.6.3.3 Receive AHB Buffers 41.6.3.4 Transmit AHB Buffers 41.6.3.5 DMA Bursting on the AHB 41.6.3.6 DMA Packet Buffer 41.6.3.7 Transmit Packet Buffer 41.6.3.8 Receive Packet Buffer 41.6.3.9 Priority Queueing in the DMA 41.6.4 MAC Transmit Block 41.6.5 MAC Receive Block 41.6.6 Checksum Offload for IP, TCP and UDP 41.6.6.1 Receiver Checksum Offload 41.6.6.2 Transmitter Checksum Offload 41.6.7 MAC Filtering Block 41.6.8 Broadcast Address 41.6.9 Hash Addressing 41.6.10 Copy all Frames (Promiscuous Mode) 41.6.11 Disable Copy of Pause Frames 41.6.12 VLAN Support 41.6.13 Wake on LAN Support 41.6.14 IEEE 1588 Support 41.6.15 Timestamp Unit 41.6.16 MAC 802.3 Pause Frame Support 41.6.16.1 802.3 Pause Frame Reception 41.6.16.2 802.3 Pause Frame Transmission 41.6.17 MAC PFC Priority-based Pause Frame Support 41.6.17.1 PFC Pause Frame Reception 41.6.17.2 PFC Pause Frame Transmission 41.6.18 Energy-efficient Ethernet Support 41.6.19 802.1Qav Support - Credit-based Shaping 41.6.20 LPI Operation in the GMAC 41.6.21 PHY Interface 41.6.22 10/100 Operation 41.6.23 Jumbo Frames 41.7 Programming Interface 41.7.1 Initialization 41.7.1.1 Configuration 41.7.1.2 Receive Buffer List 41.7.1.3 Transmit Buffer List 41.7.1.4 Address Matching 41.7.1.5 PHY Maintenance 41.7.1.6 Interrupts 41.7.1.7 Transmitting Frames 41.7.1.8 Receiving Frames 41.7.2 Statistics Registers 41.8 Ethernet MAC (GMAC) User Interface 41.8.1 GMAC Network Control Register 41.8.2 GMAC Network Configuration Register 41.8.3 GMAC Network Status Register 41.8.4 GMAC User Register 41.8.5 GMAC DMA Configuration Register 41.8.6 GMAC Transmit Status Register 41.8.7 GMAC Receive Buffer Queue Base Address Register 41.8.8 GMAC Transmit Buffer Queue Base Address Register 41.8.9 GMAC Receive Status Register 41.8.10 GMAC Interrupt Status Register 41.8.11 GMAC Interrupt Enable Register 41.8.12 GMAC Interrupt Disable Register 41.8.13 GMAC Interrupt Mask Register 41.8.14 GMAC PHY Maintenance Register 41.8.15 GMAC Receive Pause Quantum Register 41.8.16 GMAC Transmit Pause Quantum Register 41.8.17 GMAC TX Partial Store and Forward Register 41.8.18 GMAC RX Partial Store and Forward Register 41.8.19 GMAC RX Jumbo Frame Max Length Register 41.8.20 GMAC Hash Register Bottom 41.8.21 GMAC Hash Register Top 41.8.22 GMAC Specific Address 1 Bottom Register 41.8.23 GMAC Specific Address 1 Top Register 41.8.24 GMAC Specific Address 2 Bottom Register 41.8.25 GMAC Specific Address 2 Top Register 41.8.26 GMAC Specific Address 3 Bottom Register 41.8.27 GMAC Specific Address 3 Top Register 41.8.28 GMAC Specific Address 4 Bottom Register 41.8.29 GMAC Specific Address 4 Top Register 41.8.30 GMAC Type ID Match 1 Register 41.8.31 GMAC Type ID Match 2 Register 41.8.32 GMAC Type ID Match 3 Register 41.8.33 GMAC Type ID Match 4 Register 41.8.34 GMAC Wake on LAN Register 41.8.35 GMAC IPG Stretch Register 41.8.36 GMAC Stacked VLAN Register 41.8.37 GMAC Transmit PFC Pause Register 41.8.38 GMAC Specific Address 1 Mask Bottom Register 41.8.39 GMAC Specific Address Mask 1 Top Register 41.8.40 GMAC 1588 Timer Nanosecond Comparison Register 41.8.41 GMAC 1588 Timer Second Comparison Low Register 41.8.42 GMAC 1588 Timer Second Comparison High Register 41.8.43 GMAC PTP Event Frame Transmitted Seconds High Register 41.8.44 GMAC PTP Event Frame Received Seconds High Register 41.8.45 GMAC PTP Peer Event Frame Transmitted Seconds High Register 41.8.46 GMAC PTP Peer Event Frame Received Seconds High Register 41.8.47 GMAC Octets Transmitted Low Register 41.8.48 GMAC Octets Transmitted High Register 41.8.49 GMAC Frames Transmitted Register 41.8.50 GMAC Broadcast Frames Transmitted Register 41.8.51 GMAC Multicast Frames Transmitted Register 41.8.52 GMAC Pause Frames Transmitted Register 41.8.53 GMAC 64 Byte Frames Transmitted Register 41.8.54 GMAC 65 to 127 Byte Frames Transmitted Register 41.8.55 GMAC 128 to 255 Byte Frames Transmitted Register 41.8.56 GMAC 256 to 511 Byte Frames Transmitted Register 41.8.57 GMAC 512 to 1023 Byte Frames Transmitted Register 41.8.58 GMAC 1024 to 1518 Byte Frames Transmitted Register 41.8.59 GMAC Greater Than 1518 Byte Frames Transmitted Register 41.8.60 GMAC Transmit Underruns Register 41.8.61 GMAC Single Collision Frames Register 41.8.62 GMAC Multiple Collision Frames Register 41.8.63 GMAC Excessive Collisions Register 41.8.64 GMAC Late Collisions Register 41.8.65 GMAC Deferred Transmission Frames Register 41.8.66 GMAC Carrier Sense Errors Register 41.8.67 GMAC Octets Received Low Register 41.8.68 GMAC Octets Received High Register 41.8.69 GMAC Frames Received Register 41.8.70 GMAC Broadcast Frames Received Register 41.8.71 GMAC Multicast Frames Received Register 41.8.72 GMAC Pause Frames Received Register 41.8.73 GMAC 64 Byte Frames Received Register 41.8.74 GMAC 65 to 127 Byte Frames Received Register 41.8.75 GMAC 128 to 255 Byte Frames Received Register 41.8.76 GMAC 256 to 511 Byte Frames Received Register 41.8.77 GMAC 512 to 1023 Byte Frames Received Register 41.8.78 GMAC 1024 to 1518 Byte Frames Received Register 41.8.79 GMAC 1519 to Maximum Byte Frames Received Register 41.8.80 GMAC Undersized Frames Received Register 41.8.81 GMAC Oversized Frames Received Register 41.8.82 GMAC Jabbers Received Register 41.8.83 GMAC Frame Check Sequence Errors Register 41.8.84 GMAC Length Field Frame Errors Register 41.8.85 GMAC Receive Symbol Errors Register 41.8.86 GMAC Alignment Errors Register 41.8.87 GMAC Receive Resource Errors Register 41.8.88 GMAC Receive Overruns Register 41.8.89 GMAC IP Header Checksum Errors Register 41.8.90 GMAC TCP Checksum Errors Register 41.8.91 GMAC UDP Checksum Errors Register 41.8.92 GMAC 1588 Timer Increment Sub-nanoseconds Register 41.8.93 GMAC 1588 Timer Seconds High Register 41.8.94 GMAC 1588 Timer Seconds Low Register 41.8.95 GMAC 1588 Timer Nanoseconds Register 41.8.96 GMAC 1588 Timer Adjust Register 41.8.97 GMAC 1588 Timer Increment Register 41.8.98 GMAC PTP Event Frame Transmitted Seconds Low Register 41.8.99 GMAC PTP Event Frame Transmitted Nanoseconds Register 41.8.100 GMAC PTP Event Frame Received Seconds Low Register 41.8.101 GMAC PTP Event Frame Received Nanoseconds Register 41.8.102 GMAC PTP Peer Event Frame Transmitted Seconds Low Register 41.8.103 GMAC PTP Peer Event Frame Transmitted Nanoseconds Register 41.8.104 GMAC PTP Peer Event Frame Received Seconds Low Register 41.8.105 GMAC PTP Peer Event Frame Received Nanoseconds Register 41.8.106 GMAC Received LPI Transitions 41.8.107 GMAC Received LPI Time 41.8.108 GMAC Transmit LPI Transitions 41.8.109 GMAC Transmit LPI Time 41.8.110 GMAC Interrupt Status Register Priority Queue x 41.8.111 GMAC Transmit Buffer Queue Base Address Register Priority Queue x 41.8.112 GMAC Receive Buffer Queue Base Address Register Priority Queue x 41.8.113 GMAC Receive Buffer Size Register Priority Queue x 41.8.114 GMAC Credit-Based Shaping Control Register 41.8.115 GMAC Credit-Based Shaping IdleSlope Register for Queue A 41.8.116 GMAC Credit-Based Shaping IdleSlope Register for Queue B 41.8.117 GMAC Screening Type 1 Register x Priority Queue 41.8.118 GMAC Screening Type 2 Register x Priority Queue 41.8.119 GMAC Interrupt Enable Register Priority Queue x 41.8.120 GMAC Interrupt Disable Register Priority Queue x 41.8.121 GMAC Interrupt Mask Register Priority Queue x 41.8.122 GMAC Screening Type 2 EtherType Register x 41.8.123 GMAC Screening Type 2 Compare Word 0 Register x 41.8.124 GMAC Screening Type 2 Compare Word 1 Register x 42. USB High Speed Device Port (UDPHS) 42.1 Description 42.2 Embedded Characteristics 42.3 Block Diagram 42.4 Typical Connection 42.5 Product Dependencies 42.5.1 Power Management 42.5.2 Interrupt Sources 42.6 Functional Description 42.6.1 UTMI Transceivers Sharing 42.6.2 USB V2.0 High Speed Device Port Introduction 42.6.3 USB V2.0 High Speed Transfer Types 42.6.4 USB Transfer Event Definitions 42.6.5 USB V2.0 High Speed BUS Transactions 42.6.6 Endpoint Configuration 42.6.7 DPRAM Management 42.6.8 Transfer With DMA 42.6.9 Transfer Without DMA 42.6.10 Handling Transactions with USB V2.0 Device Peripheral 42.6.10.1 Setup Transaction 42.6.10.2 NYET 42.6.10.3 Data IN 42.6.10.4 Data OUT 42.6.10.5 STALL 42.6.11 Speed Identification 42.6.12 USB V2.0 High Speed Global Interrupt 42.6.13 Endpoint Interrupts 42.6.14 Power Modes 42.6.14.1 Controlling Device States 42.6.14.2 Not Powered State 42.6.14.3 Entering Attached State 42.6.14.4 From Powered State to Default State (Reset) 42.6.14.5 From Default State to Address State (Address Assigned) 42.6.14.6 From Address State to Configured State (Device Configured) 42.6.14.7 Entering Suspend State (Bus Activity) 42.6.14.8 Receiving a Host Resume 42.6.14.9 Sending an External Resume 42.6.15 Test Mode 42.7 USB High Speed Device Port (UDPHS) User Interface 42.7.1 UDPHS Control Register 42.7.2 UDPHS Frame Number Register 42.7.3 UDPHS Interrupt Enable Register 42.7.4 UDPHS Interrupt Status Register 42.7.5 UDPHS Clear Interrupt Register 42.7.6 UDPHS Endpoints Reset Register 42.7.7 UDPHS Test Register 42.7.8 UDPHS Endpoint Configuration Register 42.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) 42.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints) 42.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) 42.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint) 42.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) 42.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint) 42.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) 42.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint) 42.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) 42.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint) 42.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) 42.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint) 42.7.21 UDPHS DMA Channel Transfer Descriptor 42.7.22 UDPHS DMA Next Descriptor Address Register 42.7.23 UDPHS DMA Channel Address Register 42.7.24 UDPHS DMA Channel Control Register 42.7.25 UDPHS DMA Channel Status Register 43. USB Host High Speed Port (UHPHS) 43.1 Description 43.2 Embedded Characteristics 43.3 Block Diagram 43.4 Typical Connection 43.5 Product Dependencies 43.5.1 I/O Lines 43.5.2 Power Management 43.5.3 Interrupt Sources 43.6 Functional Description 43.6.1 EHCI 43.6.2 OHCI 43.6.3 HSIC 43.7 USB Host High Speed Port (UHPHS) User Interface 43.7.1 UHPHS Host Controller Capability Register 43.7.2 UHPHS Host Controller Structural Parameters Register 43.7.3 UHPHS Host Controller Capability Parameters Register 43.7.4 UHPHS USB Command Register 43.7.5 UHPHS USB Status Register 43.7.6 UHPHS USB Interrupt Enable Register 43.7.7 UHPHS USB Frame Index Register 43.7.8 UHPHS Control Data Structure Segment Register 43.7.9 UHPHS Periodic Frame List Base Address Register 43.7.10 UHPHS Asynchronous List Address Register 43.7.11 UHPHS Configure Flag Register 43.7.12 UHPHS Port Status and Control Register 43.7.13 EHCI: REG00 - Programmable Microframe Base Value 43.7.14 EHCI: REG01 - Programmable Packet Buffer OUT/IN Thresholds 43.7.15 EHCI: REG02 - Programmable Packet Buffer Depth 43.7.16 EHCI: REG03 43.7.17 EHCI: REG04 43.7.18 EHCI: REG05 - UTMI Configuration 43.7.19 EHCI: REG06 - AHB Error Status 43.7.20 EHCI: REG07 - AHB Master Error Address 43.7.21 EHCI: REG08 - HSIC Enable/Disable 44. Audio Class D Amplifier (CLASSD) 44.1 Description 44.2 Embedded Characteristics 44.3 Block Diagram 44.4 Pin Name List 44.5 Product Dependencies 44.5.1 I/O Lines 44.5.2 Power Management 44.5.3 Interrupt 44.6 Functional Description 44.6.1 Interpolator 44.6.1.1 Clock Configuration 44.6.1.2 CLASSD Frequency Response 44.6.2 Equalizer 44.6.3 De-emphasis Filter Frequency Response 44.6.4 Attenuator and Recommended Input Levels 44.6.5 Pulse Width Modulator (PWM) 44.6.6 Application Schematics For Use Case Examples 44.6.7 Register Write Protection 44.7 Audio Class D Amplifier (CLASSD) User Interface 44.7.1 CLASSD Control Register 44.7.2 CLASSD Mode Register 44.7.3 CLASSD Interpolator Mode Register 44.7.4 CLASSD Interpolator Status Register 44.7.5 CLASSD Transmit Holding Register 44.7.6 CLASSD Interrupt Enable Register 44.7.7 CLASSD Interrupt Disable Register 44.7.8 CLASSD Interrupt Mask Register 44.7.9 CLASSD Interrupt Status Register 44.7.10 CLASSD Write Protection Mode Register 45. Inter-IC Sound Controller (I2SC) 45.1 Description 45.2 Embedded Characteristics 45.3 Block Diagram 45.4 I/O Lines Description 45.5 Product Dependencies 45.5.1 I/O Lines 45.5.2 Power Management 45.5.3 Clocks 45.5.4 DMA Controller 45.5.5 Interrupt Sources 45.6 Functional Description 45.6.1 Initialization 45.6.2 Basic Operation 45.6.3 Master, Controller and Slave Modes 45.6.4 I2S Reception and Transmission Sequence 45.6.5 Serial Clock and Word Select Generation 45.6.6 Mono 45.6.7 Holding Registers 45.6.8 DMA Controller Operation 45.6.9 Loopback Mode 45.6.10 Interrupts 45.7 I2SC Application Examples 45.8 Inter-IC Sound Controller (I2SC) User Interface 45.8.1 I2SC Control Register 45.8.2 I2SC Mode Register 45.8.3 I2SC Status Register 45.8.4 I2SC Status Clear Register 45.8.5 I2SC Status Set Register 45.8.6 I2SC Interrupt Enable Register 45.8.7 I2SC Interrupt Disable Register 45.8.8 I2SC Interrupt Mask Register 45.8.9 I2SC Receiver Holding Register 45.8.10 I2SC Transmitter Holding Register 46. Synchronous Serial Controller (SSC) 46.1 Description 46.2 Embedded Characteristics 46.3 Block Diagram 46.4 Application Block Diagram 46.5 SSC Application Examples 46.6 Pin Name List 46.7 Product Dependencies 46.7.1 I/O Lines 46.7.2 Power Management 46.7.3 Interrupt 46.8 Functional Description 46.8.1 Clock Management 46.8.1.1 Clock Divider 46.8.1.2 Transmit Clock Management 46.8.1.3 Receive Clock Management 46.8.1.4 Serial Clock Ratio Considerations 46.8.2 Transmit Operations 46.8.3 Receive Operations 46.8.4 Start 46.8.5 Frame Synchronization 46.8.5.1 Frame Sync Data 46.8.5.2 Frame Sync Edge Detection 46.8.6 Receive Compare Modes 46.8.6.1 Compare Functions 46.8.7 Data Format 46.8.8 Loop Mode 46.8.9 Interrupt 46.8.10 Register Write Protection 46.9 Synchronous Serial Controller (SSC) User Interface 46.9.1 SSC Control Register 46.9.2 SSC Clock Mode Register 46.9.3 SSC Receive Clock Mode Register 46.9.4 SSC Receive Frame Mode Register 46.9.5 SSC Transmit Clock Mode Register 46.9.6 SSC Transmit Frame Mode Register 46.9.7 SSC Receive Holding Register 46.9.8 SSC Transmit Holding Register 46.9.9 SSC Receive Synchronization Holding Register 46.9.10 SSC Transmit Synchronization Holding Register 46.9.11 SSC Receive Compare 0 Register 46.9.12 SSC Receive Compare 1 Register 46.9.13 SSC Status Register 46.9.14 SSC Interrupt Enable Register 46.9.15 SSC Interrupt Disable Register 46.9.16 SSC Interrupt Mask Register 46.9.17 SSC Write Protection Mode Register 46.9.18 SSC Write Protection Status Register 47. Two-wire Interface (TWIHS) 47.1 Description 47.2 Embedded Characteristics 47.3 List of Abbreviations 47.4 Block Diagram 47.4.1 I/O Lines Description 47.5 Product Dependencies 47.5.1 I/O Lines 47.5.2 Power Management 47.5.3 Interrupt Sources 47.6 Functional Description 47.6.1 Transfer Format 47.6.2 Modes of Operation 47.6.3 Master Mode 47.6.3.1 Definition 47.6.3.2 Programming Master Mode 47.6.3.3 Transfer Rate Clock Source 47.6.3.4 Master Transmitter Mode 47.6.3.5 Master Receiver Mode 47.6.3.6 Internal Address 47.6.3.7 Repeated Start 47.6.3.8 Bus Clear Command 47.6.3.9 Using the DMA Controller (DMAC) in Master Mode 47.6.3.10 SMBus Mode 47.6.3.11 SMBus Quick Command (Master Mode Only) 47.6.3.12 Alternative Command 47.6.3.13 Handling Errors in Alternative Command 47.6.3.14 Read/Write Flowcharts 47.6.3.15 FIFOs 47.6.4 Multimaster Mode 47.6.4.1 Definition 47.6.4.2 Different Multimaster Modes 47.6.5 Slave Mode 47.6.5.1 Definition 47.6.5.2 Programming Slave Mode 47.6.5.3 Receiving Data 47.6.5.4 Data Transfer 47.6.5.5 Using the DMA Controller (DMAC) in Slave Mode 47.6.5.6 SMBus Mode 47.6.5.7 High-Speed Slave Mode 47.6.5.8 Alternative Command 47.6.5.9 Asynchronous Partial Wakeup (SleepWalking) 47.6.5.10 Slave Read Write Flowcharts 47.6.5.11 FIFOs 47.6.6 TWIHS Comparison Function on Received Character 47.6.7 Register Write Protection 47.7 Two-wire Interface High Speed (TWIHS) User Interface 47.7.1 TWIHS Control Register 47.7.2 TWIHS Control Register (FIFO_ENABLED) 47.7.3 TWIHS Master Mode Register 47.7.4 TWIHS Slave Mode Register 47.7.5 TWIHS Internal Address Register 47.7.6 TWIHS Clock Waveform Generator Register 47.7.7 TWIHS Status Register 47.7.8 TWIHS Status Register (FIFO_ENABLED) 47.7.9 TWIHS SMBus Timing Register 47.7.10 TWIHS Alternative Command Register 47.7.11 TWIHS Filter Register 47.7.12 TWIHS Interrupt Enable Register 47.7.13 TWIHS Interrupt Disable Register 47.7.14 TWIHS Interrupt Mask Register 47.7.15 TWIHS Receive Holding Register 47.7.16 TWIHS Receive Holding Register (FIFO_ENABLED) 47.7.17 TWIHS SleepWalking Matching Register 47.7.18 TWIHS Transmit Holding Register 47.7.19 TWIHS Transmit Holding Register (FIFO_ENABLED) 47.7.20 TWIHS FIFO Mode Register 47.7.21 TWIHS FIFO Level Register 47.7.22 TWIHS FIFO Status Register 47.7.23 TWIHS FIFO Interrupt Enable Register 47.7.24 TWIHS FIFO Interrupt Disable Register 47.7.25 TWIHS FIFO Interrupt Mask Register 47.7.26 TWIHS Write Protection Mode Register 47.7.27 TWIHS Write Protection Status Register 48. Flexible Serial Communication Controller (FLEXCOM) 48.1 Description 48.2 Embedded Characteristics 48.2.1 USART/UART Characteristics 48.2.2 SPI Characteristics 48.2.3 TWI/SMBus Characteristics 48.3 Block Diagram 48.4 I/O Lines Description 48.5 Product Dependencies 48.5.1 I/O Lines 48.5.2 Power Management 48.5.3 Interrupt Sources 48.6 Register Accesses 48.7 USART Functional Description 48.7.1 Baud Rate Generator 48.7.1.1 Baud Rate in Asynchronous Mode 48.7.1.2 Fractional Baud Rate in Asynchronous Mode 48.7.1.3 Baud Rate in Synchronous Mode or SPI Mode 48.7.1.4 Baud Rate in ISO 7816 Mode 48.7.2 Receiver and Transmitter Control 48.7.3 Synchronous and Asynchronous Modes 48.7.3.1 Transmitter Operations 48.7.3.2 Manchester Encoder 48.7.3.3 Asynchronous Receiver 48.7.3.4 Manchester Decoder 48.7.3.5 Radio Interface: Manchester Encoded USART Application 48.7.3.6 Synchronous Receiver 48.7.3.7 Receiver Operations 48.7.3.8 Parity 48.7.3.9 Multidrop Mode 48.7.3.10 Transmitter Timeguard 48.7.3.11 Receiver Timeout 48.7.3.12 Framing Error 48.7.3.13 Transmit Break 48.7.3.14 Receive Break 48.7.3.15 Hardware Handshaking 48.7.4 ISO7816 Mode 48.7.4.1 ISO7816 Mode Overview 48.7.4.2 Protocol T = 0 48.7.4.3 Protocol T = 1 48.7.5 IrDA Mode 48.7.5.1 IrDA Modulation 48.7.5.2 IrDA Baud Rate 48.7.5.3 IrDA Demodulator 48.7.6 RS485 Mode 48.7.7 USART Comparison Function on Received Character 48.7.8 SPI Mode 48.7.8.1 Modes of Operation 48.7.8.2 Bit Rate 48.7.8.3 Data Transfer 48.7.8.4 Receiver and Transmitter Control 48.7.8.5 Character Transmission 48.7.8.6 Character Reception 48.7.8.7 Receiver Timeout 48.7.9 LIN Mode 48.7.9.1 Modes of Operation 48.7.9.2 Baud Rate Configuration 48.7.9.3 Receiver and Transmitter Control 48.7.9.4 Character Transmission 48.7.9.5 Character Reception 48.7.9.6 Header Transmission (Master Node Configuration) 48.7.9.7 Header Reception (Slave Node Configuration) 48.7.9.8 Slave Node Synchronization 48.7.9.9 Identifier Parity 48.7.9.10 Node Action 48.7.9.11 Response Data Length 48.7.9.12 Checksum 48.7.9.13 Frame Slot Mode 48.7.9.14 LIN Errors 48.7.9.15 LIN Frame Handling 48.7.9.16 LIN Frame Handling with the DMAC 48.7.9.17 Wakeup Request 48.7.9.18 Bus Idle Timeout 48.7.10 Test Modes 48.7.10.1 Normal Mode 48.7.10.2 Automatic Echo Mode 48.7.10.3 Local Loopback Mode 48.7.10.4 Remote Loopback Mode 48.7.11 USART FIFOs 48.7.11.1 Overview 48.7.11.2 Sending Data with FIFO Enabled 48.7.11.3 Receiving Data with FIFO Enabled 48.7.11.4 Clearing/Flushing FIFOs 48.7.11.5 TXEMPTY, TXRDY and RXRDY Behavior 48.7.11.6 USART Single Data Mode 48.7.11.7 USART Multiple Data Mode 48.7.11.8 Transmit FIFO Lock 48.7.11.9 FIFO Pointer Error 48.7.11.10 FIFO Thresholds 48.7.11.11 FIFO Flags 48.7.12 USART Register Write Protection 48.8 SPI Functional Description 48.8.1 Modes of Operation 48.8.2 Data Transfer 48.8.3 Master Mode Operations 48.8.3.1 Master Mode Block Diagram 48.8.3.2 Master Mode Flowchart 48.8.3.3 Clock Generation 48.8.3.4 Transfer Delays 48.8.3.5 Peripheral Selection 48.8.3.6 SPI Direct Access Memory Controller (DMAC) 48.8.3.7 Peripheral Chip Select Decoding 48.8.3.8 Peripheral Deselection without DMA 48.8.3.9 Peripheral Deselection with DMA 48.8.3.10 Mode Fault Detection 48.8.4 SPI Slave Mode 48.8.5 SPI Comparison Function on Received Character 48.8.6 SPI Asynchronous and Partial Wakeup (SleepWalking) 48.8.7 SPI FIFOs 48.8.7.1 Overview 48.8.7.2 Sending Data with FIFO Enabled 48.8.7.3 Receiving Data with FIFO Enabled 48.8.7.4 Clearing/Flushing FIFOs 48.8.7.5 TXEMPTY, TDRE and RDRF Behavior 48.8.7.6 SPI Single Data Mode 48.8.7.7 SPI Multiple Data Mode 48.8.7.8 FIFO Pointer Error 48.8.7.9 FIFO Thresholds 48.8.7.10 FIFO Flags 48.8.8 SPI Register Write Protection 48.9 TWI Functional Description 48.9.1 Transfer Format 48.9.2 Modes of Operation 48.9.3 Master Mode 48.9.3.1 Definition 48.9.3.2 Programming Master Mode 48.9.3.3 Transfer Speed/Bit Rate 48.9.3.4 Master Transmitter Mode 48.9.3.5 Master Receiver Mode 48.9.3.6 Internal Address 48.9.3.7 Repeated Start 48.9.3.8 Bus Clear Command 48.9.3.9 SMBus Mode 48.9.3.10 SMBus Quick Command (Master Mode Only) 48.9.3.11 Alternative Command 48.9.3.12 Handling Errors in Alternative Command 48.9.3.13 Read/Write Flowcharts 48.9.4 Multi-Master Mode 48.9.4.1 Definition 48.9.4.2 Different Multi-Master Modes 48.9.5 Slave Mode 48.9.5.1 Definition 48.9.5.2 Programming Slave Mode 48.9.5.3 Receiving Data 48.9.5.4 Data Transfer 48.9.5.5 High-Speed Slave Mode 48.9.5.6 Alternative Command 48.9.5.7 TWI Asynchronous and Partial Wakeup (SleepWalking) 48.9.5.8 Slave Read/Write Flowcharts 48.9.6 TWI FIFOs 48.9.6.1 Overview 48.9.6.2 Sending Data with FIFO Enabled 48.9.6.3 Receiving Data with FIFO Enabled 48.9.6.4 Sending/Receiving with FIFO Enabled in Slave Mode 48.9.6.5 Clearing/Flushing FIFOs 48.9.6.6 TXRDY and RXRDY Behavior 48.9.6.7 TWI Single Data Mode 48.9.6.8 TWI Multiple Data Mode 48.9.6.9 Transmit FIFO Lock 48.9.6.10 FIFO Pointer Error 48.9.6.11 FIFO Thresholds 48.9.6.12 FIFO Flags 48.9.7 TWI Comparison Function on Received Character 48.9.8 TWI Register Write Protection 48.10 Flexible Serial Communication Unit (FLEXCOM) User Interface 48.10.1 FLEXCOM Mode Register 48.10.2 FLEXCOM Transmit Holding Register 48.10.3 FLEXCOM Receive Holding Register 48.10.4 USART Control Register 48.10.5 USART Control Register (SPI_MODE) 48.10.6 USART Mode Register 48.10.7 USART Mode Register (SPI_MODE) 48.10.8 USART Interrupt Enable Register 48.10.9 USART Interrupt Enable Register (SPI_MODE) 48.10.10 USART Interrupt Enable Register (LIN_MODE) 48.10.11 USART Interrupt Disable Register 48.10.12 USART Interrupt Disable Register (SPI_MODE) 48.10.13 USART Interrupt Disable Register (LIN_MODE) 48.10.14 USART Interrupt Mask Register 48.10.15 USART Interrupt Mask Register (SPI_MODE) 48.10.16 USART Interrupt Mask Register (LIN_MODE) 48.10.17 USART Channel Status Register 48.10.18 USART Channel Status Register (SPI_MODE) 48.10.19 USART Channel Status Register (LIN_MODE) 48.10.20 USART Receive Holding Register 48.10.21 USART Receive Holding Register (FIFO Multi Data) 48.10.22 USART Transmit Holding Register 48.10.23 USART Transmit Holding Register (FIFO Multi Data) 48.10.24 USART Baud Rate Generator Register 48.10.25 USART Receiver Timeout Register 48.10.26 USART Transmitter Timeguard Register 48.10.27 USART FI DI RATIO Register 48.10.28 USART Number of Errors Register 48.10.29 USART IrDA FILTER Register 48.10.30 USART Manchester Configuration Register 48.10.31 USART LIN Mode Register 48.10.32 USART LIN Identifier Register 48.10.33 USART LIN Baud Rate Register 48.10.34 USART Comparison Register 48.10.35 USART FIFO Mode Register 48.10.36 USART FIFO Level Register 48.10.37 USART FIFO Interrupt Enable Register 48.10.38 USART FIFO Interrupt Disable Register 48.10.39 USART FIFO Interrupt Mask Register 48.10.40 USART FIFO Event Status Register 48.10.41 USART Write Protection Mode Register 48.10.42 USART Write Protection Status Register 48.10.43 SPI Control Register 48.10.44 SPI Mode Register 48.10.45 SPI Receive Data Register 48.10.46 SPI Receive Data Register (FIFO Multiple Data, 8-bit) 48.10.47 SPI Receive Data Register (FIFO Multiple Data, 16-bit) 48.10.48 SPI Transmit Data Register 48.10.49 SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit) 48.10.50 SPI Status Register 48.10.51 SPI Interrupt Enable Register 48.10.52 SPI Interrupt Disable Register 48.10.53 SPI Interrupt Mask Register 48.10.54 SPI Chip Select Register 48.10.55 SPI FIFO Mode Register 48.10.56 SPI FIFO Level Register 48.10.57 SPI Comparison Register 48.10.58 SPI Write Protection Mode Register 48.10.59 SPI Write Protection Status Register 48.10.60 TWI Control Register 48.10.61 TWI Control Register (FIFO_ENABLED) 48.10.62 TWI Master Mode Register 48.10.63 TWI Slave Mode Register 48.10.64 TWI Internal Address Register 48.10.65 TWI Clock Waveform Generator Register 48.10.66 TWI Status Register 48.10.67 TWI Status Register (FIFO ENABLED) 48.10.68 TWI Interrupt Enable Register 48.10.69 TWI Interrupt Disable Register 48.10.70 TWI Interrupt Mask Register 48.10.71 TWI Receive Holding Register 48.10.72 TWI Receive Holding Register (FIFO Enabled) 48.10.73 TWI Transmit Holding Register 48.10.74 TWI Transmit Holding Register (FIFO Enabled) 48.10.75 TWI SMBus Timing Register 48.10.76 TWI Alternative Command Register 48.10.77 TWI Filter Register 48.10.78 TWI SleepWalking Matching Register 48.10.79 TWI FIFO Mode Register 48.10.80 TWI FIFO Level Register 48.10.81 TWI FIFO Status Register 48.10.82 TWI FIFO Interrupt Enable Register 48.10.83 TWI FIFO Interrupt Disable Register 48.10.84 TWI FIFO Interrupt Mask Register 48.10.85 TWI Write Protection Mode Register 48.10.86 TWI Write Protection Status Register 49. Universal Asynchronous Receiver Transmitter (UART) 49.1 Description 49.2 Embedded Characteristics 49.3 Block Diagram 49.4 Product Dependencies 49.4.1 I/O Lines 49.4.2 Power Management 49.4.3 Interrupt Sources 49.5 Functional Description 49.5.1 Baud Rate Generator 49.5.2 Receiver 49.5.2.1 Receiver Reset, Enable and Disable 49.5.2.2 Start Detection and Data Sampling 49.5.2.3 Receiver Ready 49.5.2.4 Receiver Overrun 49.5.2.5 Parity Error 49.5.2.6 Receiver Framing Error 49.5.2.7 Receiver Digital Filter 49.5.2.8 Receiver Timeout 49.5.3 Transmitter 49.5.3.1 Transmitter Reset, Enable and Disable 49.5.3.2 Transmit Format 49.5.3.3 Transmitter Control 49.5.4 DMA Support 49.5.5 Comparison Function on Received Character 49.5.6 Asynchronous and Partial Wakeup (SleepWalking) 49.5.7 Register Write Protection 49.5.8 Test Modes 49.6 Universal Asynchronous Receiver Transmitter (UART) User Interface 49.6.1 UART Control Register 49.6.2 UART Mode Register 49.6.3 UART Interrupt Enable Register 49.6.4 UART Interrupt Disable Register 49.6.5 UART Interrupt Mask Register 49.6.6 UART Status Register 49.6.7 UART Receiver Holding Register 49.6.8 UART Transmit Holding Register 49.6.9 UART Baud Rate Generator Register 49.6.10 UART Comparison Register 49.6.11 UART Receiver Timeout Register 49.6.12 UART Write Protection Mode Register 50. Serial Peripheral Interface (SPI) 50.1 Description 50.2 Embedded Characteristics 50.3 Block Diagram 50.4 Application Block Diagram 50.5 Signal Description 50.6 Product Dependencies 50.6.1 I/O Lines 50.6.2 Power Management 50.6.3 Interrupt 50.6.4 Direct Memory Access Controller (DMAC) 50.7 Functional Description 50.7.1 Modes of Operation 50.7.2 Data Transfer 50.7.3 Master Mode Operations 50.7.3.1 Master Mode Block Diagram 50.7.3.2 Master Mode Flow Diagram 50.7.3.3 Clock Generation 50.7.3.4 Transfer Delays 50.7.3.5 Peripheral Selection 50.7.3.6 SPI Direct Access Memory Controller (DMAC) 50.7.3.7 Peripheral Chip Select Decoding 50.7.3.8 Peripheral Deselection without DMA 50.7.3.9 Peripheral Deselection with DMA 50.7.3.10 Mode Fault Detection 50.7.4 SPI Slave Mode 50.7.5 SPI Comparison Function on Received Character 50.7.6 SPI Asynchronous and Partial Wakeup (SleepWalking) 50.7.7 FIFOs 50.7.7.1 Overview 50.7.7.2 Sending Data with FIFO Enabled 50.7.7.3 Receiving Data with FIFO Enabled 50.7.7.4 Clearing/Flushing FIFOs 50.7.7.5 TXEMPTY, TDRE and RDRF Behavior 50.7.7.6 Single Data Mode 50.7.7.7 Multiple Data Mode 50.7.7.8 FIFO Pointer Error 50.7.7.9 FIFO Thresholds 50.7.7.10 FIFO Flags 50.7.8 Register Write Protection 50.8 Serial Peripheral Interface (SPI) User Interface 50.8.1 SPI Control Register 50.8.2 SPI Mode Register 50.8.3 SPI Receive Data Register 50.8.4 SPI Receive Data Register (FIFO Multiple Data, 8-bit) 50.8.5 SPI Receive Data Register (FIFO Multiple Data, 16-bit) 50.8.6 SPI Transmit Data Register 50.8.7 SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit) 50.8.8 SPI Status Register 50.8.9 SPI Interrupt Enable Register 50.8.10 SPI Interrupt Disable Register 50.8.11 SPI Interrupt Mask Register 50.8.12 SPI Chip Select Register 50.8.13 SPI FIFO Mode Register 50.8.14 SPI FIFO Level Register 50.8.15 SPI Comparison Register 50.8.16 SPI Write Protection Mode Register 50.8.17 SPI Write Protection Status Register 51. Quad Serial Peripheral Interface (QSPI) 51.1 Description 51.2 Embedded Characteristics 51.3 Block Diagram 51.4 Signal Description 51.5 Product Dependencies 51.5.1 I/O Lines 51.5.2 Power Management 51.5.3 Interrupt Sources 51.5.4 Direct Memory Access Controller (DMA) 51.6 Functional Description 51.6.1 Serial Clock Baud Rate 51.6.2 Serial Clock Phase and Polarity 51.6.3 Transfer Delays 51.6.4 QSPI SPI Mode 51.6.4.1 SPI Mode Operations 51.6.4.2 SPI Mode Block Diagram 51.6.4.3 SPI Mode Flow Diagram 51.6.4.4 Peripheral Deselection without DMA 51.6.4.5 Peripheral Deselection with DMA 51.6.5 QSPI Serial Memory Mode 51.6.5.1 Instruction Frame 51.6.5.2 Instruction Frame Transmission 51.6.5.3 Read Memory Transfer 51.6.5.4 Continuous Read Mode 51.6.5.5 Instruction Frame Transmission Examples 51.6.6 Scrambling/Unscrambling Function 51.6.7 Register Write Protection 51.7 Quad Serial Peripheral Interface (QSPI) User Interface 51.7.1 QSPI Control Register 51.7.2 QSPI Mode Register 51.7.3 QSPI Receive Data Register 51.7.4 QSPI Transmit Data Register 51.7.5 QSPI Status Register 51.7.6 QSPI Interrupt Enable Register 51.7.7 QSPI Interrupt Disable Register 51.7.8 QSPI Interrupt Mask Register 51.7.9 QSPI Serial Clock Register 51.7.10 QSPI Instruction Address Register 51.7.11 QSPI Instruction Code Register 51.7.12 QSPI Instruction Frame Register 51.7.13 QSPI Scrambling Mode Register 51.7.14 QSPI Scrambling Key Register 51.7.15 QSPI Write Protection Mode Register 51.7.16 QSPI Write Protection Status Register 52. Secure Digital MultiMedia Card Controller (SDMMC) 52.1 Description 52.2 Embedded Characteristics 52.3 Embedded Features for SDMMC0 and SDMMC1 52.4 Reference Documents 52.5 Block Diagram 52.6 Application Block Diagram 52.7 Pin Name List 52.8 Product Dependencies 52.8.1 I/O Lines 52.8.2 Power Management 52.8.3 Interrupt Sources 52.9 SD/SDIO Operating Mode 52.10 e.MMC Operating Mode 52.10.1 Boot Operation Mode 52.10.1.1 Boot Procedure, Processor Mode 52.10.1.2 Boot Procedure, SDMA Mode 52.10.1.3 Boot Procedure, ADMA Mode 52.11 SDR104 / HS200 Tuning 52.11.1 DLL and Sampling Point 52.11.2 Retuning Method 52.11.2.1 SDMMC Tuning Sequence 52.12 I/O Calibration 52.13 Secure Digital MultiMedia Card Controller (SDMMC) User Interface 52.13.1 SDMMC SDMA System Address / Argument 2 Register 52.13.2 SDMMC Block Size Register 52.13.3 SDMMC Block Count Register 52.13.4 SDMMC Argument 1 Register 52.13.5 SDMMC Transfer Mode Register 52.13.6 SDMMC Command Register 52.13.7 SDMMC Response Register 52.13.8 SDMMC Buffer Data Port Register 52.13.9 SDMMC Present State Register 52.13.10 SDMMC Host Control 1 Register (SD_SDIO) 52.13.11 SDMMC Host Control 1 Register (e.MMC) 52.13.12 SDMMC Power Control Register 52.13.13 SDMMC Block Gap Control Register (SD_SDIO) 52.13.14 SDMMC Block Gap Control Register (e.MMC) 52.13.15 SDMMC Wakeup Control Register (SD_SDIO) 52.13.16 SDMMC Clock Control Register 52.13.17 SDMMC Timeout Control Register 52.13.18 SDMMC Software Reset Register 52.13.19 SDMMC Normal Interrupt Status Register (SD_SDIO) 52.13.20 SDMMC Normal Interrupt Status Register (e.MMC) 52.13.21 SDMMC Error Interrupt Status Register (SD_SDIO) 52.13.22 SDMMC Error Interrupt Status Register (e.MMC) 52.13.23 SDMMC Normal Interrupt Status Enable Register (SD_SDIO) 52.13.24 SDMMC Normal Interrupt Status Enable Register (e.MMC) 52.13.25 SDMMC Error Interrupt Status Enable Register (SD_SDIO) 52.13.26 SDMMC Error Interrupt Status Enable Register (e.MMC) 52.13.27 SDMMC Normal Interrupt Signal Enable Register (SD_SDIO) 52.13.28 SDMMC Normal Interrupt Signal Enable Register (e.MMC) 52.13.29 SDMMC Error Interrupt Signal Enable Register (SD_SDIO) 52.13.30 SDMMC Error Interrupt Signal Enable Register (e.MMC) 52.13.31 SDMMC Auto CMD Error Status Register 52.13.32 SDMMC Host Control 2 Register (SD_SDIO) 52.13.33 SDMMC Host Control 2 Register (e.MMC) 52.13.34 SDMMC Capabilities 0 Register 52.13.35 SDMMC Capabilities 1 Register 52.13.36 SDMMC Maximum Current Capabilities Register 52.13.37 SDMMC Force Event Register for Auto CMD Error Status 52.13.38 SDMMC Force Event Register for Error Interrupt Status 52.13.39 SDMMC ADMA Error Status Register 52.13.40 SDMMC ADMA System Address Register 52.13.41 SDMMC Preset Value Register 52.13.42 SDMMC Slot Interrupt Status Register 52.13.43 SDMMC Host Controller Version Register 52.13.44 SDMMC Additional Present State Register 52.13.45 SDMMC e.MMC Control 1 Register 52.13.46 SDMMC e.MMC Control 2 Register 52.13.47 SDMMC AHB Control Register 52.13.48 SDMMC Clock Control 2 Register 52.13.49 SDMMC Retuning Control 1 Register 52.13.50 SDMMC Retuning Control 2 Register 52.13.51 SDMMC Retuning Counter Value Register 52.13.52 SDMMC Retuning Interrupt Status Enable Register 52.13.53 SDMMC Retuning Interrupt Signal Enable Register 52.13.54 SDMMC Retuning Interrupt Status Register 52.13.55 SDMMC Retuning Status Slots Register 52.13.56 SDMMC Tuning Control Register 52.13.57 SDMMC Capabilities Control Register 52.13.58 SDMMC Calibration Control Register 53. Image Sensor Controller (ISC) 53.1 Description 53.2 Embedded Characteristics 53.3 Block Diagram and Use Cases 53.3.1 Image Sensor Controller Functional Diagrams 53.3.2 Image Sensor Controller Clock Domain Diagram 53.3.3 Image Sensor Controller Typical Use Cases 53.4 Product Dependencies 53.4.1 I/O Lines 53.4.2 Power Management 53.4.3 Interrupt Sources 53.5 Functional Description 53.5.1 ISC Clock Management 53.5.1.1 Software Requirement 53.5.2 Parallel Interface Timing Description 53.5.3 BT.601/656/1120 Embedded Timing Synchronization Operation 53.5.4 Parallel Interface External Sensor Connections 53.5.4.1 YCbCr, 10-bit CCIR656 with Embedded Synchronization 53.5.4.2 YCbCr, 8-bit CCIR656 with Embedded Synchronization 53.5.4.3 RAW Bayer Parallel Interface 53.5.4.4 Monochrome Parallel Interface 53.5.5 Parallel Front End (PFE) Module 53.5.5.1 Update the ISC Profile 53.5.5.2 Software Requirements 53.5.6 White Balance (WB) Module 53.5.7 Color Filter Array (CFA) Interpolation Module 53.5.7.1 Frame Size Requirement when Edge Interpolation is Off, ISC_CFA_CFG.EITPOL Cleared 53.5.7.2 Frame Size Requirement when Edge Interpolation is On, ISC_CFA_CFG.EITPOL Set 53.5.7.3 Bayer Mode and Edge Interpolation Description 53.5.8 Color Correction (CC) Module 53.5.9 Gamma Curve (GAM) Module 53.5.10 Color Space Conversion (CSC) Module 53.5.11 Contrast and Brightness 53.5.12 4:4:4 To 4:2:2 Chrominance Horizontal Subsampler (SUB422) Module 53.5.13 4:2:2 To 4:2:0 Chrominance Vertical Subsampler (SUB420) Module 53.5.14 Rounding, Limiting and Packing (RLP) Module 53.5.15 DMA Interface 53.5.15.1 Descriptor Memory Address Mapping 53.5.15.2 Descriptor Memory Mapping 53.5.15.3 Example: Memory Mapping for 16-bit Packed, DMA Interface IMODE = 1 at ISC_DAD0.AD0 Location 53.5.15.4 Example: Memory Mapping for 12-bit YC420SP, DMA Interface IMODE = 5 53.5.15.5 Example: Memory Mapping for 12-bit YC420P, DMA Interface IMODE = 6 53.5.16 Histogram Module 53.6 Image Sensor Controller (ISC) User Interface 53.6.1 ISC Control Enable Register 0 53.6.2 ISC Control Disable Register 0 53.6.3 ISC Control Status Register 0 53.6.4 ISC Parallel Front End Configuration 0 Register 53.6.5 ISC Parallel Front End Configuration 1 Register 53.6.6 ISC Parallel Front End Configuration 2 Register 53.6.7 ISC Clock Enable Register 53.6.8 ISC Clock Disable Register 53.6.9 ISC Clock Status Register 53.6.10 ISC Clock Configuration Register 53.6.11 ISC Interrupt Enable Register 53.6.12 ISC Interrupt Disable Register 53.6.13 ISC Interrupt Mask Register 53.6.14 ISC Interrupt Status Register 53.6.15 ISC White Balance Control Register 53.6.16 ISC White Balance Configuration Register 53.6.17 ISC White Balance Offset for R, GR Register 53.6.18 ISC White Balance Offset for B and GB Register 53.6.19 ISC White Balance Gain for R, GR Register 53.6.20 ISC White Balance Gain for B, GB Register 53.6.21 ISC Color Filter Array Control Register 53.6.22 ISC Color Filter Array Configuration Register 53.6.23 ISC Color Correction Control Register 53.6.24 ISC Color Correction RR RG Register 53.6.25 ISC Color Correction RB OR Register 53.6.26 ISC Color Correction GR GG Register 53.6.27 ISC Color Correction GB OG Register 53.6.28 ISC Color Correction BR BG Register 53.6.29 ISC Color Correction BB OB Register 53.6.30 ISC Gamma Correction Control Register 53.6.31 ISC Gamma Correction Blue Entry Register 53.6.32 ISC Gamma Correction Green Entry Register 53.6.33 ISC Gamma Correction Red Entry Register 53.6.34 ISC Color Space Conversion Control Register 53.6.35 ISC Color Space Conversion YR YG Register 53.6.36 ISC Color Space Conversion YB OY Register 53.6.37 ISC Color Space Conversion CBR CBG Register 53.6.38 ISC Color Space Conversion CBB OCB Register 53.6.39 ISC Color Space Conversion CRR CRG Register 53.6.40 ISC Color Space Conversion CRB OCR Register 53.6.41 ISC Contrast And Brightness Control Register 53.6.42 ISC Contrast And Brightness Configuration Register 53.6.43 ISC Contrast And Brightness, Brightness Register 53.6.44 ISC Contrast And Brightness, Contrast Register 53.6.45 ISC Subsampling 4:4:4 to 4:2:2 Control Register 53.6.46 ISC Subsampling 4:4:4 to 4:2:2 Configuration Register 53.6.47 ISC Subsampling 4:2:2 to 4:2:0 Control Register 53.6.48 ISC Rounding, Limiting and Packing Configuration Register 53.6.49 ISC Histogram Control Register 53.6.50 ISC Histogram Configuration Register 53.6.51 ISC DMA Configuration Register 53.6.52 ISC DMA Control Register 53.6.53 ISC DMA Descriptor Address Register 53.6.54 ISC DMA Address 0 Register 53.6.55 ISC DMA Stride 0 Register 53.6.56 ISC DMA Address 1 Register 53.6.57 ISC DMA Stride 1 Register 53.6.58 ISC DMA Address 2 Register 53.6.59 ISC DMA Stride 2 Register 53.6.60 ISC Histogram Entry 54. Controller Area Network (MCAN) 54.1 Description 54.2 Embedded Characteristics 54.3 Block Diagram 54.4 Product Dependencies 54.4.1 I/O Lines 54.4.2 Power Management 54.4.3 Interrupt Sources 54.4.4 Address Configuration 54.5 Functional Description 54.5.1 Operating Modes 54.5.1.1 Software Initialization 54.5.1.2 Normal Operation 54.5.1.3 CAN FD Operation 54.5.1.4 Transmitter Delay Compensation 54.5.1.5 Restricted Operation Mode 54.5.1.6 Bus Monitoring Mode 54.5.1.7 Disabled Automatic Retransmission 54.5.1.8 Power-down (Sleep Mode) 54.5.1.9 Test Modes 54.5.2 Timestamp Generation 54.5.3 Timeout Counter 54.5.4 Rx Handling 54.5.4.1 Acceptance Filtering 54.5.4.2 Rx FIFOs 54.5.4.3 Dedicated Rx Buffers 54.5.4.4 Debug on CAN Support 54.5.5 Tx Handling 54.5.5.1 Transmit Pause 54.5.5.2 Dedicated Tx Buffers 54.5.5.3 Tx FIFO 54.5.5.4 Tx Queue 54.5.5.5 Mixed Dedicated Tx Buffers / Tx FIFO 54.5.5.6 Mixed Dedicated Tx Buffers / Tx Queue 54.5.5.7 Transmit Cancellation 54.5.5.8 Tx Event Handling 54.5.6 FIFO Acknowledge Handling 54.5.7 Message RAM 54.5.7.1 Message RAM Configuration 54.5.7.2 Rx Buffer and FIFO Element 54.5.7.3 Tx Buffer Element 54.5.7.4 Tx Event FIFO Element 54.5.7.5 Standard Message ID Filter Element 54.5.7.6 Extended Message ID Filter Element 54.5.8 Hardware Reset Description 54.5.9 Access to Reserved Register Addresses 54.6 Controller Area Network (MCAN) User Interface 54.6.1 MCAN Core Release Register 54.6.2 MCAN Endian Register 54.6.3 MCAN Customer Register 54.6.4 MCAN Data Bit Timing and Prescaler Register 54.6.5 MCAN Test Register 54.6.6 MCAN RAM Watchdog Register 54.6.7 MCAN CC Control Register 54.6.8 MCAN Nominal Bit Timing and Prescaler Register 54.6.9 MCAN Timestamp Counter Configuration Register 54.6.10 MCAN Timestamp Counter Value Register 54.6.11 MCAN Timeout Counter Configuration Register 54.6.12 MCAN Timeout Counter Value Register 54.6.13 MCAN Error Counter Register 54.6.14 MCAN Protocol Status Register 54.6.15 MCAN Transmitter Delay Compensation Register 54.6.16 MCAN Interrupt Register 54.6.17 MCAN Interrupt Enable Register 54.6.18 MCAN Interrupt Line Select Register 54.6.19 MCAN Interrupt Line Enable 54.6.20 MCAN Global Filter Configuration 54.6.21 MCAN Standard ID Filter Configuration 54.6.22 MCAN Extended ID Filter Configuration 54.6.23 MCAN Extended ID AND Mask 54.6.24 MCAN High Priority Message Status 54.6.25 MCAN New Data 1 54.6.26 MCAN New Data 2 54.6.27 MCAN Receive FIFO 0 Configuration 54.6.28 MCAN Receive FIFO 0 Status 54.6.29 MCAN Receive FIFO 0 Acknowledge 54.6.30 MCAN Receive Buffer Configuration 54.6.31 MCAN Receive FIFO 1 Configuration 54.6.32 MCAN Receive FIFO 1 Status 54.6.33 MCAN Receive FIFO 1 Acknowledge 54.6.34 MCAN Receive Buffer / FIFO Element Size Configuration 54.6.35 MCAN Tx Buffer Configuration 54.6.36 MCAN Tx FIFO/Queue Status 54.6.37 MCAN Tx Buffer Element Size Configuration 54.6.38 MCAN Transmit Buffer Request Pending 54.6.39 MCAN Transmit Buffer Add Request 54.6.40 MCAN Transmit Buffer Cancellation Request 54.6.41 MCAN Transmit Buffer Transmission Occurred 54.6.42 MCAN Transmit Buffer Cancellation Finished 54.6.43 MCAN Transmit Buffer Transmission Interrupt Enable 54.6.44 MCAN Transmit Buffer Cancellation Finished Interrupt Enable 54.6.45 MCAN Transmit Event FIFO Configuration 54.6.46 MCAN Tx Event FIFO Status 54.6.47 MCAN Tx Event FIFO Acknowledge 55. Timer Counter (TC) 55.1 Description 55.2 Embedded Characteristics 55.3 Block Diagram 55.4 Pin List 55.5 Product Dependencies 55.5.1 I/O Lines 55.5.2 Power Management 55.5.3 Interrupt Sources 55.5.4 Synchronization Inputs from PWM 55.5.5 Fault Output 55.6 Functional Description 55.6.1 Description 55.6.2 32-bit Counter 55.6.3 Clock Selection 55.6.4 Clock Control 55.6.5 Operating Modes 55.6.6 Trigger 55.6.7 Capture Mode 55.6.8 Capture Registers A and B 55.6.9 Transfer with DMAC in Capture Mode 55.6.10 Trigger Conditions 55.6.11 Waveform Mode 55.6.12 Waveform Selection 55.6.12.1 WAVSEL = 00 55.6.12.2 WAVSEL = 10 55.6.12.3 WAVSEL = 01 55.6.12.4 WAVSEL = 11 55.6.13 External Event/Trigger Conditions 55.6.14 Synchronization with PWM 55.6.15 Output Controller 55.6.16 Quadrature Decoder 55.6.16.1 Description 55.6.16.2 Input Preprocessing 55.6.16.3 Direction Status and Change Detection 55.6.16.4 Position and Rotation Measurement 55.6.16.5 Speed Measurement 55.6.16.6 Detecting a Missing Index Pulse 55.6.16.7 Detecting Contamination/Dust at Rotary Encoder Low Speed 55.6.16.8 Missing Pulse Detection and Autocorrection 55.6.17 2-bit Gray Up/Down Counter for Stepper Motor 55.6.18 Fault Mode 55.6.19 Register Write Protection 55.7 Timer Counter (TC) User Interface 55.7.1 TC Channel Control Register 55.7.2 TC Channel Mode Register: Capture Mode 55.7.3 TC Channel Mode Register: Waveform Mode 55.7.4 TC Stepper Motor Mode Register 55.7.5 TC Register AB 55.7.6 TC Counter Value Register 55.7.7 TC Register A 55.7.8 TC Register B 55.7.9 TC Register C 55.7.10 TC Interrupt Status Register 55.7.11 TC Interrupt Enable Register 55.7.12 TC Interrupt Disable Register 55.7.13 TC Interrupt Mask Register 55.7.14 TC Extended Mode Register 55.7.15 TC Block Control Register 55.7.16 TC Block Mode Register 55.7.17 TC QDEC Interrupt Enable Register 55.7.18 TC QDEC Interrupt Disable Register 55.7.19 TC QDEC Interrupt Mask Register 55.7.20 TC QDEC Interrupt Status Register 55.7.21 TC Fault Mode Register 55.7.22 TC Write Protection Mode Register 56. Pulse Density Modulation Interface Controller (PDMIC) 56.1 Description 56.2 Embedded Characteristics 56.3 Block Diagram 56.4 Signal Description 56.5 Product Dependencies 56.5.1 I/O Lines 56.5.2 Power Management 56.5.3 Interrupt Sources 56.6 Functional Description 56.6.1 PDM Interface 56.6.1.1 Description 56.6.1.2 Startup Sequence 56.6.2 Digital Signal Processing (Digital Filter) 56.6.2.1 Description 56.6.2.2 Decimation Filter 56.6.2.3 Droop Compensation 56.6.2.4 Low Pass Filter 56.6.2.5 High Pass Filter 56.6.2.6 Gain and Offset Compensation 56.6.3 Conversion Results 56.6.4 Register Write Protection 56.7 Pulse Density Modulation Interface Controller (PDMIC) User Interface 56.7.1 PDMIC Control Register 56.7.2 PDMIC Mode Register 56.7.3 PDMIC Converted Data Register 56.7.4 PDMIC Interrupt Enable Register 56.7.5 PDMIC Interrupt Disable Register 56.7.6 PDMIC Interrupt Mask Register 56.7.7 PDMIC Interrupt Status Register 56.7.8 PDMIC DSP Configuration Register 0 56.7.9 PDMIC DSP Configuration Register 1 56.7.10 PDMIC Write Protection Mode Register 56.7.11 PDMIC Write Protection Status Register 57. Pulse Width Modulation Controller (PWM) 57.1 Description 57.2 Embedded Characteristics 57.3 Block Diagram 57.4 I/O Lines Description 57.5 Product Dependencies 57.5.1 I/O Lines 57.5.2 Power Management 57.5.3 Interrupt Sources 57.5.4 Fault Inputs 57.6 Functional Description 57.6.1 PWM Clock Generator 57.6.2 PWM Channel 57.6.2.1 Channel Block Diagram 57.6.2.2 Comparator 57.6.2.3 Trigger Selection for Timer Counter 57.6.2.4 2-bit Gray Up/Down Counter for Stepper Motor 57.6.2.5 Dead-Time Generator 57.6.2.6 Output Override 57.6.2.7 Fault Protection 57.6.2.8 Spread Spectrum Counter 57.6.2.9 Synchronous Channels 57.6.2.10 Update Time for Double-Buffering Registers 57.6.3 PWM Comparison Units 57.6.4 PWM Event Lines 57.6.5 PWM External Trigger Mode 57.6.5.1 External PWM Reset Mode 57.6.5.2 External PWM Start Mode 57.6.5.3 Cycle-By-Cycle Duty Mode 57.6.5.4 Leading-Edge Blanking (LEB) 57.6.6 PWM Controller Operations 57.6.6.1 Initialization 57.6.6.2 Source Clock Selection Criteria 57.6.6.3 Changing the Duty-Cycle, the Period and the Dead-Times 57.6.6.4 Changing the Update Period of Synchronous Channels 57.6.6.5 Changing the Comparison Value and the Comparison Configuration 57.6.6.6 Interrupt Sources 57.6.7 Register Write Protection 57.7 Pulse Width Modulation Controller (PWM) User Interface 57.7.1 PWM Clock Register 57.7.2 PWM Enable Register 57.7.3 PWM Disable Register 57.7.4 PWM Status Register 57.7.5 PWM Interrupt Enable Register 1 57.7.6 PWM Interrupt Disable Register 1 57.7.7 PWM Interrupt Mask Register 1 57.7.8 PWM Interrupt Status Register 1 57.7.9 PWM Sync Channels Mode Register 57.7.10 PWM DMA Register 57.7.11 PWM Sync Channels Update Control Register 57.7.12 PWM Sync Channels Update Period Register 57.7.13 PWM Sync Channels Update Period Update Register 57.7.14 PWM Interrupt Enable Register 2 57.7.15 PWM Interrupt Disable Register 2 57.7.16 PWM Interrupt Mask Register 2 57.7.17 PWM Interrupt Status Register 2 57.7.18 PWM Output Override Value Register 57.7.19 PWM Output Selection Register 57.7.20 PWM Output Selection Set Register 57.7.21 PWM Output Selection Clear Register 57.7.22 PWM Output Selection Set Update Register 57.7.23 PWM Output Selection Clear Update Register 57.7.24 PWM Fault Mode Register 57.7.25 PWM Fault Status Register 57.7.26 PWM Fault Clear Register 57.7.27 PWM Fault Protection Value Register 1 57.7.28 PWM Fault Protection Enable Register 57.7.29 PWM Event Line x Register 57.7.30 PWM Spread Spectrum Register 57.7.31 PWM Spread Spectrum Update Register 57.7.32 PWM Stepper Motor Mode Register 57.7.33 PWM Fault Protection Value Register 2 57.7.34 PWM Write Protection Control Register 57.7.35 PWM Write Protection Status Register 57.7.36 PWM Comparison x Value Register 57.7.37 PWM Comparison x Value Update Register 57.7.38 PWM Comparison x Mode Register 57.7.39 PWM Comparison x Mode Update Register 57.7.40 PWM Channel Mode Register 57.7.41 PWM Channel Duty Cycle Register 57.7.42 PWM Channel Duty Cycle Update Register 57.7.43 PWM Channel Period Register 57.7.44 PWM Channel Period Update Register 57.7.45 PWM Channel Counter Register 57.7.46 PWM Channel Dead Time Register 57.7.47 PWM Channel Dead Time Update Register 57.7.48 PWM Channel Mode Update Register 57.7.49 PWM External Trigger Register 57.7.50 PWM Leading-Edge Blanking Register 58. Secure Fuse Controller (SFC) 58.1 Description 58.2 Embedded Characteristics 58.3 Block Diagram 58.4 Functional Description 58.4.1 Accessing the SFC 58.4.2 Fuse Partitioning 58.4.3 Fuse Integrity Checking 58.4.4 Fuse Integrity Live Checking 58.4.5 Fuse Access 58.4.5.1 Fuse Reading 58.4.5.2 Fuse Programming 58.4.5.3 Fuse Masking 58.4.6 Fuse Functions 58.5 Secure Fuse Controller (SFC) User Interface 58.5.1 SFC Key Register 58.5.2 SFC Mode Register 58.5.3 SFC Interrupt Enable Register 58.5.4 SFC Interrupt Disable Register 58.5.5 SFC Interrupt Mask Register 58.5.6 SFC Status Register 58.5.7 SFC Data Register x 59. Integrity Check Monitor (ICM) 59.1 Description 59.2 Embedded Characteristics 59.3 Block Diagram 59.4 Product Dependencies 59.4.1 Power Management 59.4.2 Interrupt Sources 59.5 Functional Description 59.5.1 Overview 59.5.2 ICM Region Descriptor Structure 59.5.2.1 ICM Region Start Address Structure Member 59.5.2.2 ICM Region Configuration Structure Member 59.5.2.3 ICM Region Control Structure Member 59.5.2.4 ICM Region Next Address Structure Member 59.5.3 ICM Hash Area 59.5.3.1 Message Digest Example 59.5.4 Using ICM as SHA Engine 59.5.4.1 Settings for Simple SHA Calculation 59.5.4.2 Processing Period 59.5.5 ICM Automatic Monitoring Mode 59.5.6 Programming the ICM 59.5.7 Security Features 59.6 Integrity Check Monitor (ICM) User Interface 59.6.1 ICM Configuration Register 59.6.2 ICM Control Register 59.6.3 ICM Status Register 59.6.4 ICM Interrupt Enable Register 59.6.5 ICM Interrupt Disable Register 59.6.6 ICM Interrupt Mask Register 59.6.7 ICM Interrupt Status Register 59.6.8 ICM Undefined Access Status Register 59.6.9 ICM Descriptor Area Start Address Register 59.6.10 ICM Hash Area Start Address Register 59.6.11 ICM User Initial Hash Value Register 60. Advanced Encryption Standard Bridge (AESB) 60.1 Embedded Characteristics 60.2 Product Dependencies 60.2.1 Power Management 60.2.2 Interrupt 60.3 Functional Description 60.3.1 Operating Modes 60.3.2 Double Input Buffer 60.3.3 Start Modes 60.3.3.1 Manual Mode 60.3.3.2 Auto Mode 60.3.4 Last Output Data Mode 60.3.5 Manual and Auto Modes 60.3.5.1 If AESB_MR.LOD = 0 60.3.5.2 If AESB_MR.LOD = 1 60.3.6 Automatic Bridge Mode 60.3.6.1 Description 60.3.6.2 Configuration 60.3.7 Security Features 60.3.7.1 Unspecified Register Access Detection 60.4 Advanced Encryption Standard Bridge (AESB) User Interface 60.4.1 AESB Control Register 60.4.2 AESB Mode Register 60.4.3 AESB Interrupt Enable Register 60.4.4 AESB Interrupt Disable Register 60.4.5 AESB Interrupt Mask Register 60.4.6 AESB Interrupt Status Register 60.4.7 AESB Key Word Register x 60.4.8 AESB Input Data Register x 60.4.9 AESB Output Data Register x 60.4.10 AESB Initialization Vector Register x 61. Advanced Encryption Standard (AES) 61.1 Description 61.2 Embedded Characteristics 61.3 Product Dependencies 61.3.1 Power Management 61.3.2 Interrupt Sources 61.4 Functional Description 61.4.1 AES Register Endianness 61.4.2 Operating Modes 61.4.3 Double Input Buffer 61.4.4 Start Modes 61.4.4.1 Manual Mode 61.4.4.2 Auto Mode 61.4.4.3 DMA Mode 61.4.5 Last Output Data Mode 61.4.5.1 Manual and Auto Modes 61.4.5.2 DMA Mode 61.4.6 Galois/Counter Mode (GCM) 61.4.6.1 Description 61.4.6.2 Key Writing and Automatic Hash Subkey Calculation 61.4.6.3 GCM Processing 61.4.7 XEX-based Tweaked-codebook Mode (XTS) 61.4.7.1 XTS Processing Procedure 61.4.8 Automatic Padding Mode 61.4.8.1 IPSEC Padding 61.4.8.2 SSL Padding 61.4.8.3 Flags 61.4.9 Secure Protocol Layers Improved Performances 61.4.9.1 Cipher Mode 61.4.9.2 Decipher Mode 61.4.9.3 Encapsulating Security Payload (ESP) IPSec Examples 61.4.10 Security Features 61.4.10.1 Unspecified Register Access Detection 61.5 Advanced Encryption Standard (AES) User Interface 61.5.1 AES Control Register 61.5.2 AES Mode Register 61.5.3 AES Interrupt Enable Register 61.5.4 AES Interrupt Disable Register 61.5.5 AES Interrupt Mask Register 61.5.6 AES Interrupt Status Register 61.5.7 AES Key Word Register x 61.5.8 AES Input Data Register x 61.5.9 AES Output Data Register x 61.5.10 AES Initialization Vector Register x 61.5.11 AES Additional Authenticated Data Length Register 61.5.12 AES Plaintext/Ciphertext Length Register 61.5.13 AES GCM Intermediate Hash Word Register x 61.5.14 AES GCM Authentication Tag Word Register x 61.5.15 AES GCM Encryption Counter Value Register 61.5.16 AES GCM H Word Register x 61.5.17 AES Extended Mode Register 61.5.18 AES Byte Counter Register 61.5.19 AES Tweak Word Register x 61.5.20 AES Alpha Word Register x 62. Secure Hash Algorithm (SHA) 62.1 Description 62.2 Embedded Characteristics 62.3 Product Dependencies 62.3.1 Power Management 62.3.2 Interrupt Sources 62.4 Functional Description 62.4.1 SHA Algorithm 62.4.2 HMAC Algorithm 62.4.3 Processing Period 62.4.4 Double Input Buffer 62.4.5 Internal Registers for Initial Hash Value or Expected Hash Result 62.4.6 Automatic Padding 62.4.7 Automatic Check 62.4.8 Protocol Layers Improved Performances 62.4.9 Start Modes 62.4.9.1 Manual Mode 62.4.9.2 Auto Mode 62.4.9.3 DMA Mode 62.4.9.4 SHA Register Endianness 62.4.10 Security Features 62.4.10.1 Unspecified Register Access Detection 62.5 Secure Hash Algorithm (SHA) User Interface 62.5.1 SHA Control Register 62.5.2 SHA Mode Register 62.5.3 SHA Interrupt Enable Register 62.5.4 SHA Interrupt Disable Register 62.5.5 SHA Interrupt Mask Register 62.5.6 SHA Interrupt Status Register 62.5.7 SHA Message Size Register 62.5.8 SHA Bytes Count Register 62.5.9 SHA Input Data x Register 62.5.10 SHA Input/Output Data Register x 63. Triple Data Encryption Standard (TDES) 63.1 Description 63.2 Embedded Characteristics 63.3 Product Dependencies 63.3.1 Power Management 63.3.2 Interrupt Sources 63.4 Functional Description 63.4.1 Operating Modes 63.4.2 Start Modes 63.4.2.1 Manual Mode 63.4.2.2 Auto Mode 63.4.2.3 DMA Mode 63.4.3 Last Output Data Mode 63.4.3.1 Manual and Auto Modes 63.4.3.2 DMA Mode 63.4.4 Security Features 63.4.4.1 Unspecified Register Access Detection 63.5 Triple Data Encryption Standard (TDES) User Interface 63.5.1 TDES Control Register 63.5.2 TDES Mode Register 63.5.3 TDES Interrupt Enable Register 63.5.4 TDES Interrupt Disable Register 63.5.5 TDES Interrupt Mask Register 63.5.6 TDES Interrupt Status Register 63.5.7 TDES Key 1 Word Register x 63.5.8 TDES Key 2 Word Register x 63.5.9 TDES Key 3 Word Register x 63.5.10 TDES Input Data Register x 63.5.11 TDES Output Data Register x 63.5.12 TDES Initialization Vector Register x 63.5.13 TDES XTEA Rounds Register 64. True Random Number Generator (TRNG) 64.1 Description 64.2 Embedded Characteristics 64.3 Block Diagram 64.4 Product Dependencies 64.4.1 Power Management 64.4.2 Interrupt Sources 64.5 Functional Description 64.6 True Random Number Generator (TRNG) User Interface 64.6.1 TRNG Control Register 64.6.2 TRNG Interrupt Enable Register 64.6.3 TRNG Interrupt Disable Register 64.6.4 TRNG Interrupt Mask Register 64.6.5 TRNG Interrupt Status Register 64.6.6 TRNG Output Data Register 65. Security Module (SECUMOD) 65.1 Description 65.2 Embedded Characteristics 65.3 Block Diagram 65.3.1 I/O Lines Description 65.4 Product Dependencies 65.4.1 Interrupt Sources 65.5 Functional Description 65.5.1 Memory Mapping 65.5.2 Scrambling Keys 65.5.3 Internal Random Number Generator (IRNG) 65.5.4 Protection Mechanisms 65.5.4.1 PIO Backup Controller 65.5.4.2 JTAG Prevention 65.5.5 Erasing Secure Memories 65.5.5.1 BUSRAM4KB Erase Sequence 65.5.5.2 BUREG256b Erase Sequence 65.5.6 Operating Modes 65.5.6.1 Protection Unit 65.5.7 Activation or Deactivation of Protections 65.5.8 Powerup Reset 65.6 Security Module (SECUMOD) User Interface 65.6.1 SECUMOD Control Register 65.6.2 SECUMOD System Status Register 65.6.3 SECUMOD Status Register 65.6.4 SECUMOD Status Clear Register 65.6.5 SECUMOD RAM Access Ready Register 65.6.6 SECUMOD PIO Backup Register x 65.6.7 SECUMOD JTAG Protection Control Register 65.6.8 SECUMOD Scrambling Key Register 65.6.9 SECUMOD RAM Access Rights Register 65.6.10 SECUMOD RAM Access Rights Status Register 65.6.11 SECUMOD Backup Mode Protection Register 65.6.12 SECUMOD Normal Mode Protection Register 65.6.13 SECUMOD Normal Interrupt Enable Protection Register 65.6.14 SECUMOD Normal Interrupt Disable Protection Register 65.6.15 SECUMOD Normal Interrupt Mask Protection Register 65.6.16 SECUMOD Wakeup Register 66. Analog-to-Digital Converter (ADC) 66.1 Description 66.2 Embedded Characteristics 66.3 Block Diagram 66.4 Signal Description 66.5 Product Dependencies 66.5.1 Power Management 66.5.2 Interrupt Sources 66.5.3 I/O Lines 66.5.4 Hardware Triggers 66.5.5 Fault Output 66.6 Functional Description 66.6.1 Analog-to-Digital Conversion 66.6.2 ADC Clock 66.6.3 ADC Reference Voltage 66.6.4 Conversion Resolution 66.6.5 Conversion Results 66.6.6 Conversion Results Format 66.6.7 Conversion Triggers 66.6.8 Sleep Mode and Conversion Sequencer 66.6.9 Comparison Window 66.6.10 Differential and Single-ended Input Modes 66.6.10.1 Input-output Transfer Functions 66.6.11 ADC Timings 66.6.12 Last Channel Specific Measurement Trigger 66.6.13 Enhanced Resolution Mode and Digital Averaging Function 66.6.13.1 Enhanced Resolution Mode 66.6.13.2 Averaging Function versus Trigger Events 66.6.14 Automatic Error Correction 66.6.15 Touchscreen 66.6.15.1 Touchscreen Mode 66.6.15.2 4-wire Resistive Touchscreen Principles 66.6.15.3 4-wire Position Measurement Method 66.6.15.4 4-wire Pressure Measurement Method 66.6.15.5 5-wire Resistive Touchscreen Principles 66.6.15.6 5-wire Position Measurement Method 66.6.15.7 Sequence and Noise Filtering 66.6.15.8 Measured Values, Registers and Flags 66.6.15.9 Pen Detect Method 66.6.16 Asynchronous and Partial Wakeup (SleepWalking) 66.6.17 Buffer Structure 66.6.17.1 Classic ADC Channels Only (Touchscreen Disabled) 66.6.17.2 Touchscreen Channels Only 66.6.17.3 Interleaved Channels 66.6.17.4 Pen Detection Status 66.6.18 Fault Event 66.6.19 Register Write Protection 66.7 Analog-to-Digital (ADC) User Interface 66.7.1 ADC Control Register 66.7.2 ADC Mode Register 66.7.3 ADC Channel Sequence 1 Register 66.7.4 ADC Channel Sequence 2 Register 66.7.5 ADC Channel Enable Register 66.7.6 ADC Channel Disable Register 66.7.7 ADC Channel Status Register 66.7.8 ADC Last Converted Data Register 66.7.9 ADC Interrupt Enable Register 66.7.10 ADC Interrupt Disable Register 66.7.11 ADC Interrupt Mask Register 66.7.12 ADC Interrupt Status Register 66.7.13 ADC Last Channel Trigger Mode Register 66.7.14 ADC Last Channel Compare Window Register 66.7.15 ADC Overrun Status Register 66.7.16 ADC Extended Mode Register 66.7.17 ADC Compare Window Register 66.7.18 ADC Channel Offset Register 66.7.19 ADC Channel Data Register 66.7.20 ADC Analog Control Register 66.7.21 ADC Touchscreen Mode Register 66.7.22 ADC Touchscreen X Position Register 66.7.23 ADC Touchscreen Y Position Register 66.7.24 ADC Touchscreen Pressure Register 66.7.25 ADC Trigger Register 66.7.26 ADC Correction Values Register 66.7.27 ADC Channel Error Correction Register 66.7.28 ADC Touchscreen Correction Values Register 66.7.29 ADC Write Protection Mode Register 66.7.30 ADC Write Protection Status Register 67. Electrical Characteristics 67.1 Absolute Maximum Ratings 67.2 DC Characteristics 67.3 Power Consumption in Low-power Modes 67.3.1 Backup Mode 67.3.2 Backup Mode with DDR in Self-refresh 67.3.3 Ultra Low-power (ULP) Mode 67.3.3.1 ULP0 Mode 67.3.3.2 ULP1 Mode 67.3.4 Idle Mode 67.3.5 Low-power Mode Summary Table 67.3.6 Low Power Consumption Versus Modes 67.4 Clock Characteristics 67.4.1 Processor Clock Characteristics 67.4.2 Master Clock Characteristics 67.5 Oscillator Characteristics 67.5.1 Main Oscillator Characteristics 67.5.1.1 Recommended Crystal Characteristics 67.5.1.2 XIN Clock Characteristics 67.5.2 32.768 kHz Crystal Oscillator Characteristics 67.5.3 64 kHz RC Oscillator Characteristics 67.6 PLL Characteristics 67.7 USB HS Characteristics 67.7.1 Electrical Characteristics 67.7.2 Dynamic Power Consumption 67.8 PTC Characteristics 67.9 ADC Characteristics 67.9.1 ADC Power Supply 67.9.1.1 Power Supply Characteristics 67.9.2 External Reference Voltage 67.9.3 ADC Timings 67.9.4 ADC Transfer Function 67.9.4.1 Differential Mode (12-bit mode) 67.9.4.2 Single-ended Mode (12-bit mode) 67.9.4.3 Example of LSB Computation 67.9.4.4 Gain and Offset Errors 67.9.5 ADC Electrical Characteristics 67.9.6 ADC Channel Input Impedance 67.10 Analog Comparator Characteristics 67.11 SMC Timings 67.11.1 Timing Conditions 67.11.2 SMC IOSET1 Timing Extraction 67.11.2.1 SMC IOSET1 Read Timings 67.11.2.2 SMC IOSET1 Write Timings 67.11.3 SMC IOSET2 Timing Extraction 67.11.3.1 SMC IOSET2 Read Timings 67.11.3.2 SMC IOSET2 Write Timings 67.12 FLEXCOM Timings 67.12.1 FLEXCOM USART in Asynchronous Modes 67.12.2 FLEXCOM SPI Timings 67.12.2.1 Timing Conditions 67.12.2.2 Timing Extraction 67.12.3 FLEXCOM TWI Timings 67.13 USART in Asynchronous Modes 67.14 SPI Timings 67.14.1 Maximum SPI Frequency 67.14.2 Timing Conditions 67.14.3 Timing Extraction 67.15 TWI Timings 67.16 QSPI Timings 67.16.1 Maximum QSPI Frequency 67.16.2 Timing Conditions 67.16.3 Timing Extraction 67.17 MPDDRC Timings 67.17.1 Board Design Constraints 67.17.2 DDR2-SDRAM 67.17.3 LPDDR1-SDRAM 67.17.4 LPDDR2/LPDDR3-SDRAM 67.17.5 DDR3/DDR3L-SDRAM 67.18 SSC Timings 67.18.1 Timing Conditions 67.18.2 Timing Extraction 67.19 PDMIC Timings 67.19.1 Timing Conditions 67.19.2 Timing Extraction 67.20 I2SC Timings 67.20.1 Timing Conditions 67.20.2 Timing Extraction 67.21 ISC Timings 67.21.1 Timing Conditions 67.21.2 Timing Extraction 67.22 SDMMC Timings 67.23 GMAC Timings 67.23.1 Timing Conditions 67.23.2 Timing Constraints 67.23.2.1 Ethernet MAC MII Mode 67.23.2.2 Ethernet MAC RMII Mode 68. Mechanical Characteristics 68.1 289-ball LFBGA Mechanical Characteristics 69. Schematic Checklist 69.1 Power Supply 69.2 Power-On Reset 69.3 Clock, Oscillator and PLL 69.3.1 How to Define the Oscillator Load Capacitance 69.4 ICE and JTAG 69.5 Reset and Test 69.6 Shutdown/Wakeup Logic 69.7 Parallel Input/Output (PIO) 69.8 Analog-to-Digital Converter (ADC) 69.9 External Bus Interface (EBI) 69.10 USB High-Speed Host Port (UHPHS) / USB High-Speed Device Port (UDPHS) 69.11 Boot Program Hardware Constraints 69.12 Layout and Design Constraints 69.12.1 General Considerations 69.12.2 Considerations for High-Speed Differential Interfaces 69.12.3 DDR Layout and Design Considerations 69.12.4 e.MMC routing 69.12.5 USB Trace Routing Guidelines 69.12.6 QSPI Pull-up Resistors 69.12.7 Considerations for PTC Interface 70. Marking 71. Ordering Information 72. Errata 72.1 GMAC Timestamps and PTP packets 72.2 SDMMC software ‘Reset for All’ Command 72.3 FLEXCOM SMBUS 72.4 TWI/TWIHS Clear Command 72.5 SSC TD Output 72.6 I2SC First Sent Data 72.7 Quad I/O Serial Peripheral Interface (QSPI) 72.8 Master/Processor Clock Prescaler 72.9 Master CAN-FD Controller (MCAN) 72.10 MCAN Interrupt MCAN_IR.MRAF 72.11 MCAN Bus Integration State 72.12 MCAN Message RAM/RAM Arbiter 72.13 MCAN Frame Receiving 72.14 MCAN Edge Filtering 72.15 MCAN_NBTP.NTSEG2 Configuration 72.16 MCAN DAR Mode 72.17 MCAN Tx FIFO Message 72.18 MCAN High Priority Message (HPM) 72.19 ROM Code: Using JTAG IOSET 4 73. Revision History 73.1 Rev. A - 03/2018 The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV ASIA/PACIFIC
SAMA5D27C AUTO
Wakeup from up to nine wakeup pins, UART reception, analog comparison Fast wakeup capability Extended Backup mode with DDR in Self-Refresh mode • Peripherals - LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit parallel RGB - ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface - Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D amplifier - One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch) - One Pulse Density Modulation Interface Controller (PDMIC) - One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host ports (UHPHS) - One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface - One 10/100 Ethernet MAC (GMAC) Energy efficiency support (IEEE 802.3az standard) Ethernet AVB support with IEEE802.1AS time stamping IEEE802.1Qav credit-based traffic-shaping hardware support IEEE1588 Precision Time Protocol (PTP) - Two high-speed memory card hosts: SDMMC0: SD 3.0, eMMC 4.51, 8 bits SDMMC1: SD 2.0, eMMC 4.41, 4 bits only - Two master/slave Serial Peripheral Interfaces (SPI) - Two Quad Serial Peripheral Interfaces (QSPI) - Five FLEXCOMs (USART, SPI and TWI) - Five UARTs - Two master CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-triggered transmission - One Rx only UART in backup area (RXLP) - One analog comparator (ACC) in backup area - Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I2C protocol and SMBUS (TWIHS) - Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes - One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller - One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with Resistive TouchScreen capability • Safety - Zero-power Power-On Reset (POR) cells - Main crystal clock failure detector - Write-protected registers - Integrity Check Monitor (ICM) based on SHA256 - Memory Management Unit - Independent watchdog • Security - 5 Kbytes of internal scrambled SRAM: 1 Kbyte non-erasable on tamper detection 4 Kbytes erasable on tamper detection - 256 bits of scrambled and erasable registers - Up to eight tamper pins for static or dynamic intrusion detections - Secure Boot Loader(1) - On-the-fly AES encryption/decryption on DDR and QSPI memories (AESB) - RTC including time-stamping on security intrusions - Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)
Note 1:
For secure boot strategies, refer to the document “SAMA5D2 Series Secure Boot Strategy” (document no. 44040), available under Non-Disclosure Agreement (NDA). Contact a Microchip Sales Representative for details. • Hardware cryptography - SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2 - AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197 - TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3 DS60001532A-page 2 2018 Microchip Technology Inc. Document Outline Introduction Features 1. Description 2. Configuration Summary 3. Block Diagram 4. Signal Description 5. Automotive Quality Grade 6. Safety and Security Features 6.1 Design for Safety and IEC60730 Class B Certification 6.1.1 Background Information 6.2 Design for Security 6.3 Safety and IEC 60730 Features 6.4 Security Features 7. Package and Pinout 7.1 Packages 7.2 Pinouts 8. Power Considerations 8.1 Power Supplies 8.2 Powerup Considerations 8.3 Powerdown Considerations 8.4 Power Supply Sequencing at Backup Mode Entry and Exit 8.4.1 VDDBU Power Architecture 8.4.2 Backup Mode Entry 8.4.3 Backup Mode Exit (Wakeup) 9. Memories 9.1 Embedded Memories 9.1.1 Internal SRAM 9.1.2 Internal ROM 9.1.3 Boot Strategies 9.2 External Memory 9.2.1 External Bus Interface 9.2.2 Supported Memories on DDR2/DDR3/LPDDR1/LPDDR2/LPDDR3 Interface 9.2.3 Supported Memories on Static Memories and NAND Flash Interfaces 9.2.4 DDR and SDMMC I/Os Calibration 9.2.4.1 DDR I/O Calibration 9.2.4.2 SDMMC I/O Calibration 10. Event System 10.1 Real-time Event List 10.2 Real-time Event Mapping 11. System Controller 11.1 Power-On Reset 12. Peripherals 12.1 Peripheral Mapping 12.2 Peripheral Identifiers 12.3 Peripheral Signal Multiplexing on I/O Lines 12.4 Peripheral Clock Types 13. Chip Identifier (CHIPID) 13.1 Description 13.2 Embedded Characteristics 13.3 Chip Identifier (CHIPID) User Interface 13.3.1 Chip ID Register 13.3.2 Chip ID Extension Register 14. ARM Cortex-A5 14.1 Description 14.1.1 Power Management 14.1.1.1 Run Mode 14.1.1.2 Standby Mode 14.2 Embedded Characteristics 14.3 Block Diagram 14.4 Programmer Model 14.4.1 Processor Operating Modes 14.4.2 Processor Operating States 14.4.2.1 Switching State 14.4.3 Cortex-A5 Registers 14.4.3.1 CP15 Coprocessor 14.4.4 CP 15 Register Access 14.4.5 Addresses in the Cortex-A5 processor 14.4.6 Security Extensions Overview 14.4.6.1 System Boot Sequence 14.4.7 TrustZone 14.4.7.1 Hardware 14.4.7.2 Software 14.4.7.3 Debug 14.5 Memory Management Unit 14.5.1 About the MMU 14.5.2 Memory Management System 14.5.2.1 Memory types 14.5.3 TLB Organization 14.5.3.1 Micro TLB 14.5.3.2 Main TLB 14.5.4 Memory Access Sequence 14.5.5 Interaction with Memory System 14.5.6 External Aborts 14.5.6.1 External Aborts on Data Write 14.5.6.2 Synchronous and Asynchronous Aborts 14.5.7 MMU Software Accessible Registers 15. L2 Cache Controller (L2CC) 15.1 Description 15.2 Embedded Characteristics 15.3 Product Dependencies 15.3.1 Power Management 15.4 Functional Description 15.4.1 Double Linefill Issuing 15.5 L2 Cache Controller (L2CC) User Interface 15.5.1 L2CC Cache ID Register 15.5.2 L2CC Type Register 15.5.3 L2CC Control Register 15.5.4 L2CC Auxiliary Control Register 15.5.5 L2CC Tag RAM Latency Control Register 15.5.6 L2CC Data RAM Latency Control Register 15.5.7 L2CC Event Counter Control Register 15.5.8 L2CC Event Counter 1 Configuration Register 15.5.9 L2CC Event Counter 0 Configuration Register 15.5.10 L2CC Event Counter 1 Value Register 15.5.11 L2CC Event Counter 0 Value Register 15.5.12 L2CC Interrupt Mask Register 15.5.13 L2CC Masked Interrupt Status Register 15.5.14 L2CC Raw Interrupt Status Register 15.5.15 L2CC Interrupt Clear Register 15.5.16 L2CC Cache Synchronization Register 15.5.17 L2CC Invalidate Physical Address Line Register 15.5.18 L2CC Invalidate Way Register 15.5.19 L2CC Clean Physical Address Line Register 15.5.20 L2CC Clean Index Register 15.5.21 L2CC Clean Way Register 15.5.22 L2CC Clean Invalidate Physical Address Line Register 15.5.23 L2CC Clean Invalidate Index Register 15.5.24 L2CC Clean Invalidate Way Register 15.5.25 L2CC Data Lockdown Register 15.5.26 L2CC Instruction Lockdown Register 15.5.27 L2CC Debug Control Register 15.5.28 L2CC Prefetch Control Register 15.5.29 L2CC Power Control Register 16. Debug and Test Features 16.1 Description 16.2 Embedded Characteristics 16.3 Debug and Test Block Diagrams 16.4 Application Examples 16.4.1 Debug Environment 16.4.2 Test Environment 16.5 Debug and Test Pin Description 16.6 Functional Description 16.6.1 Test Pin 16.6.2 EmbeddedICE 16.6.3 JTAG Signal Description 16.6.4 Chip Access Using JTAG Connection 16.6.5 IEEE 1149.1 JTAG Boundary Scan 16.7 Boundary JTAG ID Register 16.8 Cortex-A5 DP Identification Code Register IDCODE 16.8.1 JTAG Debug Port (JTAG-DP) 16.8.2 Serial Wire Debug Port (SW-DP) 17. Standard Boot Strategies 17.1 Description 17.2 Flow Diagram 17.3 Chip Setup 17.4 Boot Configuration 17.4.1 Boot Configuration Word 17.4.2 Boot Sequence Controller Configuration Register 17.4.3 Backup Registers (BUREG) 17.4.4 Boot Configuration Word 17.4.5 NVM Boot Sequence 17.4.6 Valid Code Detection 17.4.6.1 ARM Exception Vectors Check 17.4.6.2 boot.bin File Check 17.4.7 Detailed Memory Boot Procedures 17.4.7.1 NAND Flash Boot: NAND Flash Detection 17.4.7.2 NAND Flash Boot: PMECC Error Detection and Correction 17.4.7.3 SDCard / e.MMC Boot 17.4.7.4 SPI Flash Boot 17.4.7.5 QSPI NOR Flash Boot 17.4.8 Hardware and Software Constraints 17.5 SAM-BA Monitor 17.5.1 Command List 17.5.2 UART Port 17.5.2.1 Xmodem Protocol 17.5.3 USB Device Port 17.5.3.1 Supported External Crystal / External Clocks 17.5.3.2 USB Class 17.5.3.3 Enumeration Process 17.5.3.4 Communication Endpoints 17.6 Fuse Box Controller 17.6.1 Fuse Bit Mapping 18. AXI Matrix (AXIMX) 18.1 Description 18.2 Embedded Characteristics 18.3 Operation 18.3.1 Remap 18.4 AXI Matrix (AXIMX) User Interface 18.4.1 AXI Matrix Remap Register 19. Matrix (H64MX/H32MX) 19.1 Description 19.2 Embedded Characteristics 19.3 64-bit Matrix (H64MX) 19.3.1 Matrix Masters 19.3.2 Matrix Slaves 19.3.3 Master to Slave Access 19.4 32-bit Matrix (H32MX) 19.4.1 Matrix Masters 19.4.2 Matrix Slaves 19.4.3 Master to Slave Access 19.5 Memory Mapping 19.6 Special Bus Granting Mechanism 19.7 No Default Master 19.8 Last Access Master 19.9 Fixed Default Master 19.10 Arbitration 19.10.1 Arbitration Scheduling 19.10.1.1 Undefined Length Burst Arbitration 19.10.1.2 Slot Cycle Limit Arbitration 19.10.2 Arbitration Priority Scheme 19.10.2.1 Fixed Priority Arbitration 19.10.2.2 Round-robin Arbitration 19.11 Register Write Protection 19.12 TrustZone Extension to AHB and APB 19.12.1 Security Types of AHB Slaves 19.12.1.1 Principles 19.12.1.2 Examples 19.12.2 Security of APB Slaves 19.12.3 Security Types of AHB Master Peripherals 19.12.4 Security Types of AHB Slave Peripherals 19.13 Matrix (H64MX/H32MX) User Interface 19.13.1 Bus Matrix Master Configuration Registers 19.13.2 Bus Matrix Slave Configuration Registers 19.13.3 Bus Matrix Priority Registers A For Slaves 19.13.4 Bus Matrix Priority Registers B For Slaves 19.13.5 Master Error Interrupt Enable Register 19.13.6 Master Error Interrupt Disable Register 19.13.7 Master Error Interrupt Mask Register 19.13.8 Master Error Status Register 19.13.9 Master Error Address Registers 19.13.10 Write Protection Mode Register 19.13.11 Write Protection Status Register 19.13.12 Security Slave Registers 19.13.13 Security Areas Split Slave Registers 19.13.14 Security Region Top Slave Registers 19.13.15 Security Peripheral Select x Registers 20. Special Function Registers (SFR) 20.1 Description 20.2 Embedded Characteristics 20.3 Special Function Registers (SFR) User Interface 20.3.1 DDR Configuration Register 20.3.2 OHCI Interrupt Configuration Register 20.3.3 OHCI Interrupt Status Register 20.3.4 Security Configuration Register 20.3.5 UTMI Clock Trimming Register 20.3.6 UTMI High-Speed Trimming Register 20.3.7 UTMI Full-Speed Trimming Register 20.3.8 UMTI DP/DM Pin Swapping Register 20.3.9 CAN Memories Address-based Register 20.3.10 Serial Number 0 Register 20.3.11 Serial Number 1 Register 20.3.12 AIC Interrupt Redirection Register 20.3.13 HRAMC L2CC Register 20.3.14 I2S Register 20.3.15 QSPI Clock Pad Supply Select Register 21. Special Function Registers Backup (SFRBU) 21.1 Description 21.2 Embedded Characteristics 21.3 Special Function Registers Backup (SFRBU) User Interface 21.3.1 SFRBU Power Switch BU Control Register 21.3.2 SFRBU Temperature Sensor Range Configuration Register 21.3.3 SFRBU DDR BU Mode Control Register 21.3.4 SFRBU RXLP Pull-Up Control Register 22. Advanced Interrupt Controller (AIC) 22.1 Description 22.2 Embedded Characteristics 22.3 Block Diagram 22.4 Application Block Diagram 22.5 AIC Detailed Block Diagram 22.6 I/O Line Description 22.7 Product Dependencies 22.7.1 I/O Lines 22.7.2 Power Management 22.7.3 Interrupt Sources 22.8 Functional Description 22.8.1 Interrupt Source Control 22.8.1.1 Interrupt Source Mode 22.8.1.2 Interrupt Source Enabling 22.8.1.3 Interrupt Clearing and Setting 22.8.1.4 Interrupt Status 22.8.1.5 Internal Interrupt Source Input Stage 22.8.1.6 External Interrupt Source Input Stage 22.8.2 Interrupt Latencies 22.8.2.1 External Interrupt Edge Triggered Source 22.8.2.2 External Interrupt Level Sensitive Source 22.8.2.3 Internal Interrupt Edge Triggered Source 22.8.2.4 Internal Interrupt Level Sensitive Source 22.8.3 Normal Interrupt 22.8.3.1 Priority Controller 22.8.3.2 Interrupt Nesting 22.8.3.3 Interrupt Handlers 22.8.4 Fast Interrupt 22.8.4.1 Fast Interrupt Source 22.8.4.2 Fast Interrupt Control 22.8.4.3 Fast Interrupt Handlers 22.8.5 Protect Mode 22.8.6 Spurious Interrupt 22.8.7 General Interrupt Mask 22.8.8 Register Write Protection 22.9 Advanced Interrupt Controller (AIC) User Interface 22.9.1 AIC Source Select Register 22.9.2 AIC Source Mode Register 22.9.3 AIC Source Vector Register 22.9.4 AIC Interrupt Vector Register 22.9.5 AIC FIQ Vector Register 22.9.6 AIC Interrupt Status Register 22.9.7 AIC Interrupt Pending Register 0 22.9.8 AIC Interrupt Pending Register 1 22.9.9 AIC Interrupt Pending Register 2 22.9.10 AIC Interrupt Pending Register 3 22.9.11 AIC Interrupt Mask Register 22.9.12 AIC Core Interrupt Status Register 22.9.13 AIC End of Interrupt Command Register 22.9.14 AIC Spurious Interrupt Vector Register 22.9.15 AIC Interrupt Enable Command Register 22.9.16 AIC Interrupt Disable Command Register 22.9.17 AIC Interrupt Clear Command Register 22.9.18 AIC Interrupt Set Command Register 22.9.19 AIC Debug Control Register 22.9.20 AIC Write Protection Mode Register 22.9.21 AIC Write Protection Status Register 23. Watchdog Timer (WDT) 23.1 Description 23.2 Embedded Characteristics 23.3 Block Diagram 23.4 Functional Description 23.5 Watchdog Timer (WDT) User Interface 23.5.1 Watchdog Timer Control Register 23.5.2 Watchdog Timer Mode Register 23.5.3 Watchdog Timer Status Register 24. Reset Controller (RSTC) 24.1 Description 24.2 Embedded Characteristics 24.3 Block Diagram 24.4 Functional Description 24.4.1 Reset Controller Overview 24.4.2 NRST Manager 24.4.2.1 NRST Signal or Interrupt 24.4.3 Reset States 24.4.3.1 General Reset 24.4.3.2 Wakeup Reset 24.4.3.3 User Reset 24.4.3.4 Software Reset 24.4.3.5 Watchdog Reset 24.4.4 Reset State Priorities 24.5 Reset Controller (RSTC) User Interface 24.5.1 RSTC Control Register 24.5.2 RSTC Status Register 24.5.3 RSTC Mode Register 25. Shutdown Controller (SHDWC) 25.1 Description 25.2 Embedded Characteristics 25.3 Block Diagram 25.4 I/O Lines Description 25.5 Product Dependencies 25.5.1 Power Management 25.6 Functional Description 25.6.1 Wakeup Inputs 25.7 Shutdown Controller (SHDWC) User Interface 25.7.1 Shutdown Control Register 25.7.2 Shutdown Mode Register 25.7.3 Shutdown Status Register 25.7.4 Shutdown Wakeup Inputs Register 26. Periodic Interval Timer (PIT) 26.1 Description 26.2 Embedded Characteristics 26.3 Block Diagram 26.4 Functional Description 26.5 Periodic Interval Timer (PIT) User Interface 26.5.1 PIT Mode Register 26.5.2 PIT Status Register 26.5.3 PIT Value Register 26.5.4 PIT Image Register 27. Real-time Clock (RTC) 27.1 Description 27.2 Embedded Characteristics 27.3 Block Diagram 27.4 Product Dependencies 27.4.1 Power Management 27.4.2 Interrupt 27.5 Functional Description 27.5.1 Reference Clock 27.5.2 Timing 27.5.3 Alarm 27.5.4 Error Checking when Programming 27.5.5 RTC Internal Free Running Counter Error Checking 27.5.6 Updating Time/Calendar 27.5.6.1 Gregorian and Persian Modes 27.5.6.2 UTC Mode 27.5.7 RTC Accurate Clock Calibration 27.5.8 Waveform Generation 27.5.9 Tamper Timestamping 27.6 Real-time Clock (RTC) User Interface 27.6.1 RTC Control Register 27.6.2 RTC Mode Register 27.6.3 RTC Time Register 27.6.4 RTC Time Register (UTC_MODE) 27.6.5 RTC Calendar Register 27.6.6 RTC Time Alarm Register 27.6.7 RTC Time Alarm Register (UTC_MODE) 27.6.8 RTC Calendar Alarm Register 27.6.9 RTC Calendar Alarm Register (UTC_MODE) 27.6.10 RTC Status Register 27.6.11 RTC Status Clear Command Register 27.6.12 RTC Interrupt Enable Register 27.6.13 RTC Interrupt Disable Register 27.6.14 RTC Interrupt Mask Register 27.6.15 RTC Valid Entry Register 27.6.16 RTC TimeStamp Time Register 0 27.6.17 RTC TimeStamp Time Register 0 (UTC_MODE) 27.6.18 RTC TimeStamp Time Register 1 27.6.19 RTC TimeStamp Time Register 1 (UTC_MODE) 27.6.20 RTC TimeStamp Date Register 27.6.21 RTC TimeStamp Date Register (UTC_MODE) 27.6.22 RTC TimeStamp Source Register 28. System Controller Write Protection (SYSCWP) 28.1 Functional Description 28.2 System Controller Write Protect (SYSCWP) User Interface 28.2.1 System Controller Write Protection Mode Register 29. Slow Clock Controller (SCKC) 29.1 Description 29.2 Embedded Characteristics 29.3 Block Diagram 29.4 Functional Description 29.4.1 Switching from Embedded 64 kHz RC Oscillator to 32.768 kHz Crystal Oscillator 29.4.2 Switching from 32.768 kHz Crystal Oscillator to Embedded 64 kHz RC Oscillator 29.5 Slow Clock Controller (SCKC) User Interface 29.5.1 Slow Clock Controller Configuration Register 30. Peripheral Touch Controller (PTC) 30.1 Description 30.2 Embedded Characteristics 30.3 Block Diagram 30.4 Signal Description 30.5 Product Dependencies 30.5.1 Power Management 30.5.2 I/O Lines 30.5.3 Interrupt Sources 30.6 Functional Description 30.6.1 picoPower Processor (pPP) 30.6.2 Shared Memories 30.6.2.1 Mailbox 30.6.2.2 SRAM Data Area 30.6.2.3 Firmware in SRAM Code Area 30.6.2.4 Host Interface 30.6.3 PTC Digital Controller 30.6.3.1 PTC Digital Controller Operations 30.6.4 PTC Analog Front End (AFE) 30.6.5 Operations in Mutual Capacitance 30.6.6 Operations in Self-capacitance 30.7 Peripheral Touch Controller (PTC) User Interface 30.7.1 PTC Command Register 30.7.2 PTC Interrupt Status Register 30.7.3 PTC Enable Register 31. Low Power Asynchronous Receiver (RXLP) 31.1 Description 31.2 Embedded Characteristics 31.3 Block Diagram 31.4 Product Dependencies 31.4.1 Power Management 31.5 Functional Description 31.5.1 Baud Rate Generator 31.5.2 Receiver 31.5.2.1 Receiver Reset, Enable and Disable 31.5.2.2 Start Detection and Data Sampling 31.5.2.3 Parity Error 31.5.2.4 Receiver Framing Error 31.5.2.5 Receiver Digital Filter 31.5.3 Comparison Function on Received Character 31.5.4 Register Write Protection 31.6 Low Power Asynchronous Receiver (RXLP) User Interface 31.6.1 RXLP Control Register 31.6.2 RXLP Mode Register 31.6.3 RXLP Receiver Holding Register 31.6.4 RXLP Baud Rate Generator Register 31.6.5 RXLP Comparison Register 31.6.6 RXLP Write Protection Mode Register 32. Analog Comparator Controller (ACC) 32.1 Description 32.2 Embedded Characteristics 32.3 Block Diagram 32.4 Signal Description 32.5 Product Dependencies 32.5.1 I/O Lines 32.5.2 Power Management 32.6 Functional Description 32.6.1 Description 32.6.2 Register Write Protection 32.7 Analog Comparator Controller (ACC) User Interface 32.7.1 ACC Control Register 32.7.2 ACC Mode Register 32.7.3 ACC Write Protection Mode Register 32.7.4 ACC Write Protection Status Register 33. Clock Generator 33.1 Description 33.2 Embedded Characteristics 33.3 Block Diagram 33.4 Slow Clock 33.4.1 Embedded 64 kHz (typical) RC Oscillator 33.4.2 32.768 kHz Crystal Oscillator 33.5 Main Clock 33.5.1 12 MHz RC Oscillator 33.5.2 12 MHz RC Oscillator Clock Frequency Adjustment 33.5.3 8 to 24 MHz Crystal Oscillator 33.5.4 Main Clock Source Selection 33.5.5 Bypassing the 8 to 24 MHz Crystal Oscillator 33.5.6 Main Frequency Counter 33.5.7 Switching Main Clock Between the RC Oscillator and the Crystal Oscillator 33.6 Divider and PLLA Block 33.6.1 Divider and Phase Lock Loop Programming 33.7 UTMI PLL Clock 33.8 Audio PLL 34. Power Management Controller (PMC) 34.1 Description 34.2 Embedded Characteristics 34.3 Block Diagram 34.4 Master Clock Controller 34.5 Processor Clock Controller 34.6 Matrix Clock Controller 34.7 Programmable Clock Controller 34.8 Core and Bus Independent Clocks for Peripherals 34.9 Peripheral and Generic Clock Controller 34.10 LCDC Clock Controller 34.11 ISC Clock Controller 34.12 USB Device and Host Clocks 34.13 DDR2/LPDDR/LPDDR2 Clock Controller 34.14 Fast Startup from Ultra Low-power (ULP) Mode 0 34.15 Fast Startup from Ultra Low-Power (ULP) Mode 1 34.16 Asynchronous Partial Wakeup (SleepWalking) 34.16.1 Description 34.16.2 Configuration Procedure 34.17 Main Crystal Oscillator Failure Detection 34.18 32.768 kHz Crystal Oscillator Frequency Monitor 34.19 Programming Sequence 34.20 Clock Switching Details 34.20.1 Master Clock Switching Timings 34.20.2 Clock Switching Waveforms 34.21 Register Write Protection 34.22 Power Management Controller (PMC) User Interface 34.22.1 PMC System Clock Enable Register 34.22.2 PMC System Clock Disable Register 34.22.3 PMC System Clock Status Register 34.22.4 PMC Peripheral Clock Enable Register 0 34.22.5 PMC Peripheral Clock Disable Register 0 34.22.6 PMC Peripheral Clock Status Register 0 34.22.7 PMC UTMI Clock Configuration Register 34.22.8 PMC Clock Generator Main Oscillator Register 34.22.9 PMC Clock Generator Main Clock Frequency Register 34.22.10 PMC Clock Generator PLLA Register 34.22.11 PMC Master Clock Register 34.22.12 PMC USB Clock Register 34.22.13 PMC Programmable Clock Register 34.22.14 PMC Interrupt Enable Register 34.22.15 PMC Interrupt Disable Register 34.22.16 PMC Status Register 34.22.17 PMC Interrupt Mask Register 34.22.18 PMC Fast Startup Polarity Register 34.22.19 PMC Fast Startup Mode Register 34.22.20 PMC Fault Output Clear Register 34.22.21 PLL Charge Pump Current Register 34.22.22 PMC Write Protection Mode Register 34.22.23 PMC Write Protection Status Register 34.22.24 PMC Peripheral Clock Enable Register 1 34.22.25 PMC Peripheral Clock Disable Register 1 34.22.26 PMC Peripheral Clock Status Register 1 34.22.27 PMC Peripheral Control Register 34.22.28 PMC Oscillator Calibration Register 34.22.29 PMC SleepWalking Enable Register 0 34.22.30 PMC SleepWalking Disable Register 0 34.22.31 PMC SleepWalking Status Register 0 34.22.32 PMC SleepWalking Activity Status Register 0 34.22.33 PMC SleepWalking Enable Register 1 34.22.34 PMC SleepWalking Disable Register 1 34.22.35 PMC SleepWalking Status Register 1 34.22.36 PMC SleepWalking Activity Status Register 1 34.22.37 PMC SleepWalking Activity In Progress Register 34.22.38 PMC SleepWalking Control Register 34.22.39 PMC Audio PLL Control Register 0 34.22.40 PMC Audio PLL Control Register 1 35. Parallel Input/Output Controller (PIO) 35.1 Description 35.2 Embedded Characteristics 35.3 Block Diagram 35.4 Product Dependencies 35.4.1 Pin Multiplexing 35.4.2 External Interrupt Lines 35.4.3 Power Management 35.4.4 Interrupt Generation 35.5 Functional Description 35.5.1 I/O Line Configuration Method 35.5.1.1 Security Management 35.5.1.2 Programming I/O Line Configuration 35.5.1.3 Reading I/O line configuration 35.5.2 Pull-up and Pull-down Resistor Control 35.5.3 General Purpose or Peripheral Function Selection 35.5.4 Output Control 35.5.5 Synchronous Data Output 35.5.6 Open-Drain Mode 35.5.7 Output Line Timings 35.5.8 Inputs 35.5.9 Input Glitch and Debouncing Filters 35.5.10 Input Edge/Level Interrupt 35.5.11 Interrupt Management 35.5.12 I/O Lines Lock 35.5.13 Programmable I/O Drive 35.5.14 Programmable Schmitt Trigger 35.5.15 I/O Line Configuration Freeze 35.5.15.1 Software Freeze 35.5.16 Register Write Protection 35.6 I/O Lines Programming Example 35.7 Parallel Input/Output Controller (PIO) User Interface 35.7.1 PIO Mask Register 35.7.2 PIO Configuration Register 35.7.3 PIO Pin Data Status Register 35.7.4 PIO Lock Status Register 35.7.5 PIO Set Output Data Register 35.7.6 PIO Clear Output Data Register 35.7.7 PIO Output Data Status Register 35.7.8 PIO Interrupt Enable Register 35.7.9 PIO Interrupt Disable Register 35.7.10 PIO Interrupt Mask Register 35.7.11 PIO Interrupt Status Register 35.7.12 PIO I/O Freeze Configuration Register 35.7.13 PIO Write Protection Mode Register 35.7.14 PIO Write Protection Status Register 35.7.15 Secure PIO Mask Register 35.7.16 Secure PIO Configuration Register 35.7.17 Secure PIO Pin Data Status Register 35.7.18 Secure PIO Lock Status Register 35.7.19 Secure PIO Set Output Data Register 35.7.20 Secure PIO Clear Output Data Register 35.7.21 Secure PIO Output Data Status Register 35.7.22 Secure PIO Interrupt Enable Register 35.7.23 Secure PIO Interrupt Disable Register 35.7.24 Secure PIO Interrupt Mask Register 35.7.25 Secure PIO Interrupt Status Register 35.7.26 Secure PIO Set I/O Non-Secure Register 35.7.27 Secure PIO Set I/O Secure Register 35.7.28 Secure PIO I/O Security Status Register 35.7.29 Secure PIO I/O Freeze Configuration Register 35.7.30 Secure PIO Slow Clock Divider Debouncing Register 35.7.31 Secure PIO Write Protection Mode Register 35.7.32 Secure PIO Write Protection Status Register 36. External Memories 36.1 Multiport DDR-SDRAM Controller (MPDDRC) 36.1.1 Description 36.1.2 MPDDR Controller Block Diagram 36.1.3 I/O Lines Description 36.1.4 Product Dependencies 36.1.5 Implementation Example 36.1.5.1 16-bit DDR2 36.1.5.2 2x16-bit DDR2 36.1.5.3 16-bit DDR3/DDR3L 36.1.5.4 2x16-bit DDR3/DDR3L 36.1.5.5 2x16-bit LPDDR2/LPDDR3 36.2 External Bus Interface (EBI) 36.2.1 Description 36.2.2 Implementation Examples 36.2.2.1 8-bit NAND Flash 36.2.2.2 16-bit NAND Flash 36.2.2.3 NOR Flash on NCS0 37. Multiport DDR-SDRAM Controller (MPDDRC) 37.1 Description 37.2 Embedded Characteristics 37.3 MPDDRC Module Diagram 37.4 Product Dependencies, Initialization Sequence 37.4.1 Low-power DDR1-SDRAM Initialization 37.4.2 DDR2-SDRAM Initialization 37.4.3 Low-power DDR2-SDRAM Initialization 37.4.4 DDR3-SDRAM/DDR3L-SDRAM Initialization 37.4.5 Low-power DDR3-SDRAM Initialization 37.5 Functional Description 37.5.1 DDR-SDRAM Controller Write Cycle 37.5.2 DDR-SDRAM Controller Read Cycle 37.5.2.1 All Banks Autorefresh 37.5.2.2 Per-bank Autorefresh 37.5.2.3 Adjust Autorefresh Rate 37.5.3 Power Management 37.5.3.1 Self-refresh Mode 37.5.3.2 Powerdown Mode 37.5.3.3 Deep Powerdown Mode 37.5.3.4 Change Frequency During Self-Refresh Mode with Low-power DDR-SDRAM Devices and DDR3-SDRAM 37.5.3.5 Reset Mode 37.5.4 Multiport Functionality 37.5.4.1 Round-robin Arbitration 37.5.4.2 Request-word Weighted Round-robin Arbitration 37.5.4.3 Bandwidth Weighted Round-robin Arbitration 37.5.5 Scrambling/Unscrambling Function 37.5.6 Register Write Protection 37.6 Software Interface/SDRAM Organization, Address Mapping 37.6.1 DDR-SDRAM Address Mapping for 16-bit Memory Data Bus Width 37.6.2 DDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width 37.6.3 DDR-SDRAM Address Mapping for Low-cost Memories 37.7 AHB Multiport DDR-SDRAM Controller (MPDDRC) User Interface 37.7.1 MPDDRC Mode Register 37.7.2 MPDDRC Refresh Timer Register 37.7.3 MPDDRC Configuration Register 37.7.4 MPDDRC Timing Parameter 0 Register 37.7.5 MPDDRC Timing Parameter 1 Register 37.7.6 MPDDRC Timing Parameter 2 Register 37.7.7 MPDDRC Low-Power Register 37.7.8 MPDDRC Memory Device Register 37.7.9 MPDDRC Low-power DDR2 Low-power DDR3 Low-power Register 37.7.10 MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Calibration and MR4 Register 37.7.11 MPDDRC Low-power DDR2 Low-power DDR3 and DDR3 Timing Calibration Register 37.7.12 MPDDRC I/O Calibration Register 37.7.13 MPDDRC OCMS Register 37.7.14 MPDDRC OCMS KEY1 Register 37.7.15 MPDDRC OCMS KEY2 Register 37.7.16 MPDDRC Configuration Arbiter Register 37.7.17 MPDDRC Timeout Register 37.7.18 MPDDRC Request Port 0-1-2-3 Register 37.7.19 MPDDRC Request Port 4-5-6-7 Register 37.7.20 MPDDRC Current/Maximum Bandwidth Port 0-1-2-3 Register 37.7.21 MPDDRC Current/Maximum Bandwidth Port 4-5-6-7 Register 37.7.22 MPDDRC Read Data Path Register 37.7.23 MPDDRC Monitor Configuration Register 37.7.24 MPDDRC Monitor Address High/Low Port x Register 37.7.25 MPDDRC Monitor Information Port x Register (MAX_WAIT) 37.7.26 MPDDRC Monitor Information Port x Register (NB_TRANSFERS) 37.7.27 MPDDRC Monitor Information Port x Register (TOTAL_LATENCY) 37.7.28 MPDDRC Write Protection Mode Register 37.7.29 MPDDRC Write Protection Status Register 38. Static Memory Controller (SMC) 38.1 Description 38.2 Embedded Characteristics 38.3 Block Diagram 38.4 I/O Lines Description 38.5 Multiplexed Signals 38.6 Application Example 38.6.1 Hardware Interface 38.7 Product Dependencies 38.7.1 I/O Lines 38.7.2 Power Management 38.7.3 Interrupt Sources 38.8 External Memory Mapping 38.9 Connection to External Devices 38.9.1 Data Bus Width 38.9.2 Byte Write or Byte Select Access 38.9.2.1 Byte Write Access 38.9.2.2 Byte Select Access 38.9.2.3 Signal Multiplexing 38.10 Standard Read and Write Protocols 38.10.1 Read Waveforms 38.10.1.1 NRD Waveform 38.10.1.2 NCS Waveform 38.10.1.3 Read Cycle 38.10.2 Read Mode 38.10.2.1 Read is Controlled by NRD (READ_MODE = 1) 38.10.2.2 Read is Controlled by NCS (READ_MODE = 0) 38.10.3 Write Waveforms 38.10.3.1 NWE Waveforms 38.10.3.2 NCS Waveforms 38.10.3.3 Write Cycle 38.10.4 Write Mode 38.10.4.1 Write is Controlled by NWE (WRITE_MODE = 1) 38.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0) 38.10.5 Coding Timing Parameters 38.10.6 Reset Values of Timing Parameters 38.10.7 Usage Restriction 38.10.7.1 For Read Operations 38.10.7.2 For Write Operations 38.10.7.3 For Read and Write Operations 38.11 Scrambling/Unscrambling Function 38.12 Automatic Wait States 38.12.1 Chip Select Wait States 38.12.2 Early Read Wait State 38.12.3 Reload User Configuration Wait State 38.12.3.1 User Procedure 38.12.3.2 Slow Clock Mode Transition 38.12.4 Read to Write Wait State 38.13 Data Float Wait States 38.13.1 READ_MODE 38.13.2 TDF Optimization Enabled (TDF_MODE = 1) 38.13.3 TDF Optimization Disabled (TDF_MODE = 0) 38.14 External Wait 38.14.1 Restriction 38.14.2 Frozen Mode 38.14.3 Ready Mode 38.14.4 NWAIT Latency and Read/Write Timings 38.15 Slow Clock Mode 38.15.1 Slow Clock Mode Waveforms 38.15.2 Switching from (to) Slow Clock Mode to (from) Normal Mode 38.16 Register Write Protection 38.17 NFC Operations 38.17.1 NFC Overview 38.17.2 NFC Control Registers 38.17.2.1 Building NFC Address Command Example 38.17.2.2 NFC Address Command 38.17.2.3 NFC Data Address 38.17.2.4 NFC DATA Status 38.17.3 NFC Initialization 38.17.3.1 NFC Timing Engine 38.17.4 NFC SRAM 38.17.4.1 NFC SRAM Mapping 38.17.4.2 NFC SRAM Access Prioritization Algorithm 38.17.5 NAND Flash Operations 38.17.5.1 Page Read 38.17.5.2 Program Page 38.18 PMECC Controller Functional Description 38.18.1 MLC/SLC Write Page Operation Using PMECC 38.18.1.1 SLC/MLC Write Operation with Spare Enable Bit Set 38.18.1.2 SLC/MLC Write Operation with Spare Disable 38.18.2 MLC/SLC Read Page Operation Using PMECC 38.18.2.1 MLC/SLC Read Operation with Spare Decoding 38.18.2.2 MLC/SLC Read Operation 38.18.2.3 MLC/SLC User Read ECC Area 38.18.2.4 MLC Controller Working with NFC 38.19 Software Implementation 38.19.1 Remainder Substitution Procedure 38.19.2 Finding the Error Location Polynomial Sigma(x) 38.19.3 Finding the Error Position 38.19.3.1 Error Location 38.20 Static Memory Controller (SMC) User Interface 38.20.1 NFC Configuration Register 38.20.2 NFC Control Register 38.20.3 NFC Status Register 38.20.4 NFC Interrupt Enable Register 38.20.5 NFC Interrupt Disable Register 38.20.6 NFC Interrupt Mask Register 38.20.7 NFC Address Cycle Zero Register 38.20.8 NFC Bank Register 38.20.9 PMECC Configuration Register 38.20.10 PMECC Spare Area Size Register 38.20.11 PMECC Start Address Register 38.20.12 PMECC End Address Register 38.20.13 PMECC Control Register 38.20.14 PMECC Status Register 38.20.15 PMECC Interrupt Enable Register 38.20.16 PMECC Interrupt Disable Register 38.20.17 PMECC Interrupt Mask Register 38.20.18 PMECC Interrupt Status Register 38.20.19 PMECC Redundancy x Register 38.20.20 PMECC Remainder x Register 38.20.21 PMECC Error Location Configuration Register 38.20.22 PMECC Error Location Primitive Register 38.20.23 PMECC Error Location Enable Register 38.20.24 PMECC Error Location Disable Register 38.20.25 PMECC Error Location Status Register 38.20.26 PMECC Error Location Interrupt Enable Register 38.20.27 PMECC Error Location Interrupt Disable Register 38.20.28 PMECC Error Location Interrupt Mask Register 38.20.29 PMECC Error Location Interrupt Status Register 38.20.30 PMECC Error Location SIGMA0 Register 38.20.31 PMECC Error Location SIGMAx Register 38.20.32 PMECC Error Location x Register 38.20.33 Setup Register 38.20.34 Pulse Register 38.20.35 Cycle Register 38.20.36 Timings Register 38.20.37 Mode Register 38.20.38 Off Chip Memory Scrambling Register 38.20.39 Off Chip Memory Scrambling Key1 Register 38.20.40 Off Chip Memory Scrambling Key2 Register 38.20.41 Write Protection Mode Register 38.20.42 Write Protection Status Register 39. DMA Controller (XDMAC) 39.1 Description 39.2 Embedded Characteristics 39.3 Block Diagram 39.4 DMA Controller Peripheral Connections 39.5 Functional Description 39.5.1 Basic Definitions 39.5.2 Transfer Hierarchy Diagram 39.5.3 Peripheral Synchronized Transfer 39.5.3.1 Software Triggered Synchronized Transfer 39.5.4 XDMAC Transfer Software Operation 39.5.4.1 Single Block With Single Microblock Transfer 39.5.4.2 Single Block Transfer With Multiple Microblock 39.5.4.3 Master Transfer 39.5.4.4 Disabling A Channel Before Transfer Completion 39.6 Linked List Descriptor Operation 39.6.1 Linked List Descriptor View 39.6.1.1 Channel Next Descriptor View 0–3 Structures 39.6.2 Descriptor Structure Members Description 39.6.2.1 Descriptor Structure Microblock Control Member 39.7 XDMAC Maintenance Software Operations 39.7.1 Disabling a Channel 39.7.2 Suspending a Channel 39.7.3 Flushing a Channel 39.7.4 Maintenance Operation Priority 39.7.4.1 Disable Operation Priority 39.7.4.2 Flush Operation Priority 39.7.4.3 Suspend Operation Priority 39.8 XDMAC Software Requirements 39.9 Extensible DMA Controller (XDMAC) User Interface 39.9.1 XDMAC Global Type Register 39.9.2 XDMAC Global Configuration Register 39.9.3 XDMAC Global Weighted Arbiter Configuration Register 39.9.4 XDMAC Global Interrupt Enable Register 39.9.5 XDMAC Global Interrupt Disable Register 39.9.6 XDMAC Global Interrupt Mask Register 39.9.7 XDMAC Global Interrupt Status Register 39.9.8 XDMAC Global Channel Enable Register 39.9.9 XDMAC Global Channel Disable Register 39.9.10 XDMAC Global Channel Status Register 39.9.11 XDMAC Global Channel Read Suspend Register 39.9.12 XDMAC Global Channel Write Suspend Register 39.9.13 XDMAC Global Channel Read Write Suspend Register 39.9.14 XDMAC Global Channel Read Write Resume Register 39.9.15 XDMAC Global Channel Software Request Register 39.9.16 XDMAC Global Channel Software Request Status Register 39.9.17 XDMAC Global Channel Software Flush Request Register 39.9.18 XDMAC Channel x [x = 0..15] Interrupt Enable Register 39.9.19 XDMAC Channel x [x = 0..15] Interrupt Disable Register 39.9.20 XDMAC Channel x [x = 0..15] Interrupt Mask Register 39.9.21 XDMAC Channel x [x = 0..15] Interrupt Status Register 39.9.22 XDMAC Channel x [x = 0..15] Source Address Register 39.9.23 XDMAC Channel x [x = 0..15] Destination Address Register 39.9.24 XDMAC Channel x [x = 0..15] Next Descriptor Address Register 39.9.25 XDMAC Channel x [x = 0..15] Next Descriptor Control Register 39.9.26 XDMAC Channel x [x = 0..15] Microblock Control Register 39.9.27 XDMAC Channel x [x = 0..15] Block Control Register 39.9.28 XDMAC Channel x [x = 0..15] Configuration Register 39.9.29 XDMAC Channel x [x = 0..15] Data Stride Memory Set Pattern Register 39.9.30 XDMAC Channel x [x = 0..15] Source Microblock Stride Register 39.9.31 XDMAC Channel x [x = 0..15] Destination Microblock Stride Register 40. LCD Controller (LCDC) 40.1 Description 40.2 Embedded Characteristics 40.3 Block Diagram 40.4 I/O Lines Description 40.5 Product Dependencies 40.5.1 I/O Lines 40.5.2 Power Management 40.5.3 Interrupt Sources 40.6 Functional Description 40.6.1 Timing Engine Configuration 40.6.1.1 Pixel Clock Period Configuration 40.6.1.2 Horizontal and Vertical Synchronization Configuration 40.6.1.3 Timing Engine Powerup Software Operation 40.6.1.4 Timing Engine Powerdown Software Operation 40.6.2 DMA Software Operations 40.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure 40.6.2.2 Enabling a DMA Channel 40.6.2.3 Disabling a DMA Channel 40.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor 40.6.2.5 DMA Interrupt Generation 40.6.2.6 DMA Address Alignment Requirements 40.6.3 Overlay Software Configuration 40.6.3.1 System Bus Access Attributes 40.6.3.2 Color Attributes 40.6.3.3 Window Position, Size, Scaling and Striding Attributes 40.6.3.4 Overlay Blender Attributes 40.6.3.5 Overlay Attributes Software Operation 40.6.4 RGB Frame Buffer Memory Bitmap 40.6.4.1 1 bpp Through Color Lookup Table 40.6.4.2 2 bpp Through Color Lookup Table 40.6.4.3 4 bpp Through Color Lookup Table 40.6.4.4 8 bpp Through Color Lookup Table 40.6.4.5 12 bpp Memory Mapping, RGB 4:4:4 40.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 40.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 40.6.4.8 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5 40.6.4.9 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5 40.6.4.10 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6 40.6.4.11 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 40.6.4.12 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6 40.6.4.13 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6 40.6.4.14 24 bpp Unpacked Memory Mapping, RGB 8:8:8 40.6.4.15 24 bpp Packed Memory Mapping, RGB 8:8:8 40.6.4.16 25 bpp Memory Mapping, ARGB 1:8:8:8 40.6.4.17 32 bpp Memory Mapping, ARGB 8:8:8:8 40.6.4.18 32 bpp Memory Mapping, RGBA 8:8:8:8 40.6.5 YUV Frame Buffer Memory Mapping 40.6.5.1 AYCbCr 4:4:4 Interleaved Frame Buffer Memory Mapping 40.6.5.2 4:2:2 Interleaved Mode Frame Buffer Memory Mapping 40.6.5.3 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping 40.6.5.4 4:2:2 Planar Mode Frame Buffer Memory Mapping 40.6.5.5 4:2:0 Planar Mode Frame Buffer Memory Mapping 40.6.5.6 4:2:0 Semiplanar Frame Buffer Memory Mapping 40.6.6 Chrominance Upsampling Unit 40.6.6.1 Chrominance Upsampling Algorithm 40.6.7 Line and Pixel Striding 40.6.7.1 Line Striding 40.6.7.2 Pixel Striding 40.6.8 Color Space Conversion Unit 40.6.9 Two-Dimension Scaler 40.6.9.1 Video Scaler Description 40.6.9.2 Horizontal Scaler 40.6.9.3 Vertical Scaler 40.6.10 Color Combine Unit 40.6.10.1 Window Overlay 40.6.10.2 Base Layer with Window Overlay Optimization 40.6.10.3 Overlay Blending 40.6.10.4 Window Blending 40.6.10.5 Color Keying 40.6.11 LCDC PWM Controller 40.6.12 Post Processing Controller 40.6.13 LCD Overall Performance 40.6.13.1 Color Lookup Table (CLUT) 40.6.13.2 RGB Mode Fetch Performance 40.6.13.3 YUV Mode Fetch Performance 40.6.14 Input FIFO 40.6.15 Output FIFO 40.6.16 Output Timing Generation 40.6.16.1 Active Display Timing Mode 40.6.17 Output Format 40.6.17.1 Active Mode Output Pin Assignment 40.7 LCD Controller (LCDC) User Interface 40.7.1 LCD Controller Configuration Register 0 40.7.2 LCD Controller Configuration Register 1 40.7.3 LCD Controller Configuration Register 2 40.7.4 LCD Controller Configuration Register 3 40.7.5 LCD Controller Configuration Register 4 40.7.6 LCD Controller Configuration Register 5 40.7.7 LCD Controller Configuration Register 6 40.7.8 LCD Controller Enable Register 40.7.9 LCD Controller Disable Register 40.7.10 LCD Controller Status Register 40.7.11 LCD Controller Interrupt Enable Register 40.7.12 LCD Controller Interrupt Disable Register 40.7.13 LCD Controller Interrupt Mask Register 40.7.14 LCD Controller Interrupt Status Register 40.7.15 LCD Controller Attribute Register 40.7.16 Base Layer Channel Enable Register 40.7.17 Base Layer Channel Disable Register 40.7.18 Base Layer Channel Status Register 40.7.19 Base Layer Interrupt Enable Register 40.7.20 Base Layer Interrupt Disable Register 40.7.21 Base Layer Interrupt Mask Register 40.7.22 Base Layer Interrupt Status Register 40.7.23 Base DMA Head Register 40.7.24 Base DMA Address Register 40.7.25 Base DMA Control Register 40.7.26 Base DMA Next Register 40.7.27 Base Layer Configuration Register 0 40.7.28 Base Layer Configuration Register 1 40.7.29 Base Layer Configuration Register 2 40.7.30 Base Layer Configuration Register 3 40.7.31 Base Layer Configuration Register 4 40.7.32 Base Layer Configuration Register 5 40.7.33 Base Layer Configuration Register 6 40.7.34 Overlay 1 Channel Enable Register 40.7.35 Overlay 1 Channel Disable Register 40.7.36 Overlay 1 Channel Status Register 40.7.37 Overlay 1 Interrupt Enable Register 40.7.38 Overlay 1 Interrupt Disable Register 40.7.39 Overlay 1 Interrupt Mask Register 40.7.40 Overlay 1 Interrupt Status Register 40.7.41 Overlay 1 Head Register 40.7.42 Overlay 1 Address Register 40.7.43 Overlay 1 Control Register 40.7.44 Overlay 1 Next Register 40.7.45 Overlay 1 Configuration Register 0 40.7.46 Overlay 1 Configuration Register 1 40.7.47 Overlay 1 Configuration Register 2 40.7.48 Overlay 1 Configuration Register 3 40.7.49 Overlay 1 Configuration Register 4 40.7.50 Overlay 1 Configuration Register 5 40.7.51 Overlay 1 Configuration Register 6 40.7.52 Overlay 1 Configuration Register 7 40.7.53 Overlay 1 Configuration Register 8 40.7.54 Overlay 1 Configuration Register 9 40.7.55 Overlay 2 Channel Enable Register 40.7.56 Overlay 2 Channel Disable Register 40.7.57 Overlay 2 Channel Status Register 40.7.58 Overlay 2 Interrupt Enable Register 40.7.59 Overlay 2 Interrupt Disable Register 40.7.60 Overlay 2 Interrupt Mask Register 40.7.61 Overlay 2 Interrupt Status Register 40.7.62 Overlay 2 Head Register 40.7.63 Overlay 2 Address Register 40.7.64 Overlay 2 Control Register 40.7.65 Overlay 2 Next Register 40.7.66 Overlay 2 Configuration Register 0 40.7.67 Overlay 2 Configuration Register 1 40.7.68 Overlay 2 Configuration Register 2 40.7.69 Overlay 2 Configuration Register 3 40.7.70 Overlay 2 Configuration Register 4 40.7.71 Overlay 2 Configuration Register 5 40.7.72 Overlay 2 Configuration Register 6 40.7.73 Overlay 2 Configuration Register 7 40.7.74 Overlay 2 Configuration Register 8 40.7.75 Overlay 2 Configuration Register 9 40.7.76 High-End Overlay Channel Enable Register 40.7.77 High-End Overlay Channel Disable Register 40.7.78 High-End Overlay Channel Status Register 40.7.79 High-End Overlay Interrupt Enable Register 40.7.80 High-End Overlay Interrupt Disable Register 40.7.81 High-End Overlay Interrupt Mask Register 40.7.82 High-End Overlay Interrupt Status Register 40.7.83 High-End Overlay DMA Head Register 40.7.84 High-End Overlay DMA Address Register 40.7.85 High-End Overlay DMA Control Register 40.7.86 High-End Overlay DMA Next Register 40.7.87 High-End Overlay U-UV DMA Head Register 40.7.88 High-End Overlay U-UV DMA Address Register 40.7.89 High-End Overlay U-UV DMA Control Register 40.7.90 High-End Overlay U-UV DMA Next Register 40.7.91 High-End Overlay V DMA Head Register 40.7.92 High-End Overlay V DMA Address Register 40.7.93 High-End Overlay V DMA Control Register 40.7.94 High-End Overlay V DMA Next Register 40.7.95 High-End Overlay Configuration Register 0 40.7.96 High-End Overlay Configuration Register 1 40.7.97 High-End Overlay Configuration Register 2 40.7.98 High-End Overlay Configuration Register 3 40.7.99 High-End Overlay Configuration Register 4 40.7.100 High-End Overlay Configuration Register 5 40.7.101 High-End Overlay Configuration Register 6 40.7.102 High-End Overlay Configuration Register 7 40.7.103 High-End Overlay Configuration Register 8 40.7.104 High-End Overlay Configuration Register 9 40.7.105 High-End Overlay Configuration Register 10 40.7.106 High-End Overlay Configuration Register 11 40.7.107 High-End Overlay Configuration Register 12 40.7.108 High-End Overlay Configuration Register 13 40.7.109 High-End Overlay Configuration Register 14 40.7.110 High-End Overlay Configuration Register 15 40.7.111 High-End Overlay Configuration Register 16 40.7.112 High-End Overlay Configuration Register 17 40.7.113 High-End Overlay Configuration Register 18 40.7.114 High-End Overlay Configuration Register 19 40.7.115 High-End Overlay Configuration Register 20 40.7.116 High-End Overlay Configuration Register 21 40.7.117 High-End Overlay Configuration Register 22 40.7.118 High-End Overlay Configuration Register 23 40.7.119 High-End Overlay Configuration Register 24 40.7.120 High-End Overlay Configuration Register 25 40.7.121 High-End Overlay Configuration Register 26 40.7.122 High-End Overlay Configuration Register 27 40.7.123 High-End Overlay Configuration Register 28 40.7.124 High-End Overlay Configuration Register 29 40.7.125 High-End Overlay Configuration Register 30 40.7.126 High-End Overlay Configuration Register 31 40.7.127 High-End Overlay Configuration Register 32 40.7.128 High-End Overlay Configuration Register 33 40.7.129 High-End Overlay Configuration Register 34 40.7.130 High-End Overlay Configuration Register 35 40.7.131 High-End Overlay Configuration Register 36 40.7.132 High-End Overlay Configuration Register 37 40.7.133 High-End Overlay Configuration Register 38 40.7.134 High-End Overlay Configuration Register 39 40.7.135 High-End Overlay Configuration Register 40 40.7.136 High-End Overlay Configuration Register 41 40.7.137 Post Processing Channel Enable Register 40.7.138 Post Processing Channel Disable Register 40.7.139 Post Processing Channel Status Register 40.7.140 Post Processing Interrupt Enable Register 40.7.141 Post Processing Interrupt Disable Register 40.7.142 Post Processing Interrupt Mask Register 40.7.143 Post Processing Interrupt Status Register 40.7.144 Post Processing Head Register 40.7.145 Post Processing Address Register 40.7.146 Post Processing Control Register 40.7.147 Post Processing Next Register 40.7.148 Post Processing Configuration Register 0 40.7.149 Post Processing Configuration Register 1 40.7.150 Post Processing Configuration Register 2 40.7.151 Post Processing Configuration Register 3 40.7.152 Post Processing Configuration Register 4 40.7.153 Post Processing Configuration Register 5 40.7.154 Base CLUT Register x 40.7.155 Overlay 1 CLUT Register x 40.7.156 Overlay 2 CLUT Register x 40.7.157 High-End Overlay CLUT Register x 41. Ethernet MAC (GMAC) 41.1 Description 41.2 Embedded Characteristics 41.3 Block Diagram 41.4 Signal Interfaces 41.5 Product Dependencies 41.5.1 I/O Lines 41.5.2 Power Management 41.5.3 Interrupt Sources 41.6 Functional Description 41.6.1 Media Access Controller 41.6.2 1588 Timestamp Unit 41.6.3 AHB Direct Memory Access Interface 41.6.3.1 Packet Buffer DMA 41.6.3.2 Partial Store and Forward Using Packet Buffer DMA 41.6.3.3 Receive AHB Buffers 41.6.3.4 Transmit AHB Buffers 41.6.3.5 DMA Bursting on the AHB 41.6.3.6 DMA Packet Buffer 41.6.3.7 Transmit Packet Buffer 41.6.3.8 Receive Packet Buffer 41.6.3.9 Priority Queueing in the DMA 41.6.4 MAC Transmit Block 41.6.5 MAC Receive Block 41.6.6 Checksum Offload for IP, TCP and UDP 41.6.6.1 Receiver Checksum Offload 41.6.6.2 Transmitter Checksum Offload 41.6.7 MAC Filtering Block 41.6.8 Broadcast Address 41.6.9 Hash Addressing 41.6.10 Copy all Frames (Promiscuous Mode) 41.6.11 Disable Copy of Pause Frames 41.6.12 VLAN Support 41.6.13 Wake on LAN Support 41.6.14 IEEE 1588 Support 41.6.15 Timestamp Unit 41.6.16 MAC 802.3 Pause Frame Support 41.6.16.1 802.3 Pause Frame Reception 41.6.16.2 802.3 Pause Frame Transmission 41.6.17 MAC PFC Priority-based Pause Frame Support 41.6.17.1 PFC Pause Frame Reception 41.6.17.2 PFC Pause Frame Transmission 41.6.18 Energy-efficient Ethernet Support 41.6.19 802.1Qav Support - Credit-based Shaping 41.6.20 LPI Operation in the GMAC 41.6.21 PHY Interface 41.6.22 10/100 Operation 41.6.23 Jumbo Frames 41.7 Programming Interface 41.7.1 Initialization 41.7.1.1 Configuration 41.7.1.2 Receive Buffer List 41.7.1.3 Transmit Buffer List 41.7.1.4 Address Matching 41.7.1.5 PHY Maintenance 41.7.1.6 Interrupts 41.7.1.7 Transmitting Frames 41.7.1.8 Receiving Frames 41.7.2 Statistics Registers 41.8 Ethernet MAC (GMAC) User Interface 41.8.1 GMAC Network Control Register 41.8.2 GMAC Network Configuration Register 41.8.3 GMAC Network Status Register 41.8.4 GMAC User Register 41.8.5 GMAC DMA Configuration Register 41.8.6 GMAC Transmit Status Register 41.8.7 GMAC Receive Buffer Queue Base Address Register 41.8.8 GMAC Transmit Buffer Queue Base Address Register 41.8.9 GMAC Receive Status Register 41.8.10 GMAC Interrupt Status Register 41.8.11 GMAC Interrupt Enable Register 41.8.12 GMAC Interrupt Disable Register 41.8.13 GMAC Interrupt Mask Register 41.8.14 GMAC PHY Maintenance Register 41.8.15 GMAC Receive Pause Quantum Register 41.8.16 GMAC Transmit Pause Quantum Register 41.8.17 GMAC TX Partial Store and Forward Register 41.8.18 GMAC RX Partial Store and Forward Register 41.8.19 GMAC RX Jumbo Frame Max Length Register 41.8.20 GMAC Hash Register Bottom 41.8.21 GMAC Hash Register Top 41.8.22 GMAC Specific Address 1 Bottom Register 41.8.23 GMAC Specific Address 1 Top Register 41.8.24 GMAC Specific Address 2 Bottom Register 41.8.25 GMAC Specific Address 2 Top Register 41.8.26 GMAC Specific Address 3 Bottom Register 41.8.27 GMAC Specific Address 3 Top Register 41.8.28 GMAC Specific Address 4 Bottom Register 41.8.29 GMAC Specific Address 4 Top Register 41.8.30 GMAC Type ID Match 1 Register 41.8.31 GMAC Type ID Match 2 Register 41.8.32 GMAC Type ID Match 3 Register 41.8.33 GMAC Type ID Match 4 Register 41.8.34 GMAC Wake on LAN Register 41.8.35 GMAC IPG Stretch Register 41.8.36 GMAC Stacked VLAN Register 41.8.37 GMAC Transmit PFC Pause Register 41.8.38 GMAC Specific Address 1 Mask Bottom Register 41.8.39 GMAC Specific Address Mask 1 Top Register 41.8.40 GMAC 1588 Timer Nanosecond Comparison Register 41.8.41 GMAC 1588 Timer Second Comparison Low Register 41.8.42 GMAC 1588 Timer Second Comparison High Register 41.8.43 GMAC PTP Event Frame Transmitted Seconds High Register 41.8.44 GMAC PTP Event Frame Received Seconds High Register 41.8.45 GMAC PTP Peer Event Frame Transmitted Seconds High Register 41.8.46 GMAC PTP Peer Event Frame Received Seconds High Register 41.8.47 GMAC Octets Transmitted Low Register 41.8.48 GMAC Octets Transmitted High Register 41.8.49 GMAC Frames Transmitted Register 41.8.50 GMAC Broadcast Frames Transmitted Register 41.8.51 GMAC Multicast Frames Transmitted Register 41.8.52 GMAC Pause Frames Transmitted Register 41.8.53 GMAC 64 Byte Frames Transmitted Register 41.8.54 GMAC 65 to 127 Byte Frames Transmitted Register 41.8.55 GMAC 128 to 255 Byte Frames Transmitted Register 41.8.56 GMAC 256 to 511 Byte Frames Transmitted Register 41.8.57 GMAC 512 to 1023 Byte Frames Transmitted Register 41.8.58 GMAC 1024 to 1518 Byte Frames Transmitted Register 41.8.59 GMAC Greater Than 1518 Byte Frames Transmitted Register 41.8.60 GMAC Transmit Underruns Register 41.8.61 GMAC Single Collision Frames Register 41.8.62 GMAC Multiple Collision Frames Register 41.8.63 GMAC Excessive Collisions Register 41.8.64 GMAC Late Collisions Register 41.8.65 GMAC Deferred Transmission Frames Register 41.8.66 GMAC Carrier Sense Errors Register 41.8.67 GMAC Octets Received Low Register 41.8.68 GMAC Octets Received High Register 41.8.69 GMAC Frames Received Register 41.8.70 GMAC Broadcast Frames Received Register 41.8.71 GMAC Multicast Frames Received Register 41.8.72 GMAC Pause Frames Received Register 41.8.73 GMAC 64 Byte Frames Received Register 41.8.74 GMAC 65 to 127 Byte Frames Received Register 41.8.75 GMAC 128 to 255 Byte Frames Received Register 41.8.76 GMAC 256 to 511 Byte Frames Received Register 41.8.77 GMAC 512 to 1023 Byte Frames Received Register 41.8.78 GMAC 1024 to 1518 Byte Frames Received Register 41.8.79 GMAC 1519 to Maximum Byte Frames Received Register 41.8.80 GMAC Undersized Frames Received Register 41.8.81 GMAC Oversized Frames Received Register 41.8.82 GMAC Jabbers Received Register 41.8.83 GMAC Frame Check Sequence Errors Register 41.8.84 GMAC Length Field Frame Errors Register 41.8.85 GMAC Receive Symbol Errors Register 41.8.86 GMAC Alignment Errors Register 41.8.87 GMAC Receive Resource Errors Register 41.8.88 GMAC Receive Overruns Register 41.8.89 GMAC IP Header Checksum Errors Register 41.8.90 GMAC TCP Checksum Errors Register 41.8.91 GMAC UDP Checksum Errors Register 41.8.92 GMAC 1588 Timer Increment Sub-nanoseconds Register 41.8.93 GMAC 1588 Timer Seconds High Register 41.8.94 GMAC 1588 Timer Seconds Low Register 41.8.95 GMAC 1588 Timer Nanoseconds Register 41.8.96 GMAC 1588 Timer Adjust Register 41.8.97 GMAC 1588 Timer Increment Register 41.8.98 GMAC PTP Event Frame Transmitted Seconds Low Register 41.8.99 GMAC PTP Event Frame Transmitted Nanoseconds Register 41.8.100 GMAC PTP Event Frame Received Seconds Low Register 41.8.101 GMAC PTP Event Frame Received Nanoseconds Register 41.8.102 GMAC PTP Peer Event Frame Transmitted Seconds Low Register 41.8.103 GMAC PTP Peer Event Frame Transmitted Nanoseconds Register 41.8.104 GMAC PTP Peer Event Frame Received Seconds Low Register 41.8.105 GMAC PTP Peer Event Frame Received Nanoseconds Register 41.8.106 GMAC Received LPI Transitions 41.8.107 GMAC Received LPI Time 41.8.108 GMAC Transmit LPI Transitions 41.8.109 GMAC Transmit LPI Time 41.8.110 GMAC Interrupt Status Register Priority Queue x 41.8.111 GMAC Transmit Buffer Queue Base Address Register Priority Queue x 41.8.112 GMAC Receive Buffer Queue Base Address Register Priority Queue x 41.8.113 GMAC Receive Buffer Size Register Priority Queue x 41.8.114 GMAC Credit-Based Shaping Control Register 41.8.115 GMAC Credit-Based Shaping IdleSlope Register for Queue A 41.8.116 GMAC Credit-Based Shaping IdleSlope Register for Queue B 41.8.117 GMAC Screening Type 1 Register x Priority Queue 41.8.118 GMAC Screening Type 2 Register x Priority Queue 41.8.119 GMAC Interrupt Enable Register Priority Queue x 41.8.120 GMAC Interrupt Disable Register Priority Queue x 41.8.121 GMAC Interrupt Mask Register Priority Queue x 41.8.122 GMAC Screening Type 2 EtherType Register x 41.8.123 GMAC Screening Type 2 Compare Word 0 Register x 41.8.124 GMAC Screening Type 2 Compare Word 1 Register x 42. USB High Speed Device Port (UDPHS) 42.1 Description 42.2 Embedded Characteristics 42.3 Block Diagram 42.4 Typical Connection 42.5 Product Dependencies 42.5.1 Power Management 42.5.2 Interrupt Sources 42.6 Functional Description 42.6.1 UTMI Transceivers Sharing 42.6.2 USB V2.0 High Speed Device Port Introduction 42.6.3 USB V2.0 High Speed Transfer Types 42.6.4 USB Transfer Event Definitions 42.6.5 USB V2.0 High Speed BUS Transactions 42.6.6 Endpoint Configuration 42.6.7 DPRAM Management 42.6.8 Transfer With DMA 42.6.9 Transfer Without DMA 42.6.10 Handling Transactions with USB V2.0 Device Peripheral 42.6.10.1 Setup Transaction 42.6.10.2 NYET 42.6.10.3 Data IN 42.6.10.4 Data OUT 42.6.10.5 STALL 42.6.11 Speed Identification 42.6.12 USB V2.0 High Speed Global Interrupt 42.6.13 Endpoint Interrupts 42.6.14 Power Modes 42.6.14.1 Controlling Device States 42.6.14.2 Not Powered State 42.6.14.3 Entering Attached State 42.6.14.4 From Powered State to Default State (Reset) 42.6.14.5 From Default State to Address State (Address Assigned) 42.6.14.6 From Address State to Configured State (Device Configured) 42.6.14.7 Entering Suspend State (Bus Activity) 42.6.14.8 Receiving a Host Resume 42.6.14.9 Sending an External Resume 42.6.15 Test Mode 42.7 USB High Speed Device Port (UDPHS) User Interface 42.7.1 UDPHS Control Register 42.7.2 UDPHS Frame Number Register 42.7.3 UDPHS Interrupt Enable Register 42.7.4 UDPHS Interrupt Status Register 42.7.5 UDPHS Clear Interrupt Register 42.7.6 UDPHS Endpoints Reset Register 42.7.7 UDPHS Test Register 42.7.8 UDPHS Endpoint Configuration Register 42.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) 42.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints) 42.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) 42.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint) 42.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) 42.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint) 42.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) 42.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint) 42.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) 42.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint) 42.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) 42.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint) 42.7.21 UDPHS DMA Channel Transfer Descriptor 42.7.22 UDPHS DMA Next Descriptor Address Register 42.7.23 UDPHS DMA Channel Address Register 42.7.24 UDPHS DMA Channel Control Register 42.7.25 UDPHS DMA Channel Status Register 43. USB Host High Speed Port (UHPHS) 43.1 Description 43.2 Embedded Characteristics 43.3 Block Diagram 43.4 Typical Connection 43.5 Product Dependencies 43.5.1 I/O Lines 43.5.2 Power Management 43.5.3 Interrupt Sources 43.6 Functional Description 43.6.1 EHCI 43.6.2 OHCI 43.6.3 HSIC 43.7 USB Host High Speed Port (UHPHS) User Interface 43.7.1 UHPHS Host Controller Capability Register 43.7.2 UHPHS Host Controller Structural Parameters Register 43.7.3 UHPHS Host Controller Capability Parameters Register 43.7.4 UHPHS USB Command Register 43.7.5 UHPHS USB Status Register 43.7.6 UHPHS USB Interrupt Enable Register 43.7.7 UHPHS USB Frame Index Register 43.7.8 UHPHS Control Data Structure Segment Register 43.7.9 UHPHS Periodic Frame List Base Address Register 43.7.10 UHPHS Asynchronous List Address Register 43.7.11 UHPHS Configure Flag Register 43.7.12 UHPHS Port Status and Control Register 43.7.13 EHCI: REG00 - Programmable Microframe Base Value 43.7.14 EHCI: REG01 - Programmable Packet Buffer OUT/IN Thresholds 43.7.15 EHCI: REG02 - Programmable Packet Buffer Depth 43.7.16 EHCI: REG03 43.7.17 EHCI: REG04 43.7.18 EHCI: REG05 - UTMI Configuration 43.7.19 EHCI: REG06 - AHB Error Status 43.7.20 EHCI: REG07 - AHB Master Error Address 43.7.21 EHCI: REG08 - HSIC Enable/Disable 44. Audio Class D Amplifier (CLASSD) 44.1 Description 44.2 Embedded Characteristics 44.3 Block Diagram 44.4 Pin Name List 44.5 Product Dependencies 44.5.1 I/O Lines 44.5.2 Power Management 44.5.3 Interrupt 44.6 Functional Description 44.6.1 Interpolator 44.6.1.1 Clock Configuration 44.6.1.2 CLASSD Frequency Response 44.6.2 Equalizer 44.6.3 De-emphasis Filter Frequency Response 44.6.4 Attenuator and Recommended Input Levels 44.6.5 Pulse Width Modulator (PWM) 44.6.6 Application Schematics For Use Case Examples 44.6.7 Register Write Protection 44.7 Audio Class D Amplifier (CLASSD) User Interface 44.7.1 CLASSD Control Register 44.7.2 CLASSD Mode Register 44.7.3 CLASSD Interpolator Mode Register 44.7.4 CLASSD Interpolator Status Register 44.7.5 CLASSD Transmit Holding Register 44.7.6 CLASSD Interrupt Enable Register 44.7.7 CLASSD Interrupt Disable Register 44.7.8 CLASSD Interrupt Mask Register 44.7.9 CLASSD Interrupt Status Register 44.7.10 CLASSD Write Protection Mode Register 45. Inter-IC Sound Controller (I2SC) 45.1 Description 45.2 Embedded Characteristics 45.3 Block Diagram 45.4 I/O Lines Description 45.5 Product Dependencies 45.5.1 I/O Lines 45.5.2 Power Management 45.5.3 Clocks 45.5.4 DMA Controller 45.5.5 Interrupt Sources 45.6 Functional Description 45.6.1 Initialization 45.6.2 Basic Operation 45.6.3 Master, Controller and Slave Modes 45.6.4 I2S Reception and Transmission Sequence 45.6.5 Serial Clock and Word Select Generation 45.6.6 Mono 45.6.7 Holding Registers 45.6.8 DMA Controller Operation 45.6.9 Loopback Mode 45.6.10 Interrupts 45.7 I2SC Application Examples 45.8 Inter-IC Sound Controller (I2SC) User Interface 45.8.1 I2SC Control Register 45.8.2 I2SC Mode Register 45.8.3 I2SC Status Register 45.8.4 I2SC Status Clear Register 45.8.5 I2SC Status Set Register 45.8.6 I2SC Interrupt Enable Register 45.8.7 I2SC Interrupt Disable Register 45.8.8 I2SC Interrupt Mask Register 45.8.9 I2SC Receiver Holding Register 45.8.10 I2SC Transmitter Holding Register 46. Synchronous Serial Controller (SSC) 46.1 Description 46.2 Embedded Characteristics 46.3 Block Diagram 46.4 Application Block Diagram 46.5 SSC Application Examples 46.6 Pin Name List 46.7 Product Dependencies 46.7.1 I/O Lines 46.7.2 Power Management 46.7.3 Interrupt 46.8 Functional Description 46.8.1 Clock Management 46.8.1.1 Clock Divider 46.8.1.2 Transmit Clock Management 46.8.1.3 Receive Clock Management 46.8.1.4 Serial Clock Ratio Considerations 46.8.2 Transmit Operations 46.8.3 Receive Operations 46.8.4 Start 46.8.5 Frame Synchronization 46.8.5.1 Frame Sync Data 46.8.5.2 Frame Sync Edge Detection 46.8.6 Receive Compare Modes 46.8.6.1 Compare Functions 46.8.7 Data Format 46.8.8 Loop Mode 46.8.9 Interrupt 46.8.10 Register Write Protection 46.9 Synchronous Serial Controller (SSC) User Interface 46.9.1 SSC Control Register 46.9.2 SSC Clock Mode Register 46.9.3 SSC Receive Clock Mode Register 46.9.4 SSC Receive Frame Mode Register 46.9.5 SSC Transmit Clock Mode Register 46.9.6 SSC Transmit Frame Mode Register 46.9.7 SSC Receive Holding Register 46.9.8 SSC Transmit Holding Register 46.9.9 SSC Receive Synchronization Holding Register 46.9.10 SSC Transmit Synchronization Holding Register 46.9.11 SSC Receive Compare 0 Register 46.9.12 SSC Receive Compare 1 Register 46.9.13 SSC Status Register 46.9.14 SSC Interrupt Enable Register 46.9.15 SSC Interrupt Disable Register 46.9.16 SSC Interrupt Mask Register 46.9.17 SSC Write Protection Mode Register 46.9.18 SSC Write Protection Status Register 47. Two-wire Interface (TWIHS) 47.1 Description 47.2 Embedded Characteristics 47.3 List of Abbreviations 47.4 Block Diagram 47.4.1 I/O Lines Description 47.5 Product Dependencies 47.5.1 I/O Lines 47.5.2 Power Management 47.5.3 Interrupt Sources 47.6 Functional Description 47.6.1 Transfer Format 47.6.2 Modes of Operation 47.6.3 Master Mode 47.6.3.1 Definition 47.6.3.2 Programming Master Mode 47.6.3.3 Transfer Rate Clock Source 47.6.3.4 Master Transmitter Mode 47.6.3.5 Master Receiver Mode 47.6.3.6 Internal Address 47.6.3.7 Repeated Start 47.6.3.8 Bus Clear Command 47.6.3.9 Using the DMA Controller (DMAC) in Master Mode 47.6.3.10 SMBus Mode 47.6.3.11 SMBus Quick Command (Master Mode Only) 47.6.3.12 Alternative Command 47.6.3.13 Handling Errors in Alternative Command 47.6.3.14 Read/Write Flowcharts 47.6.3.15 FIFOs 47.6.4 Multimaster Mode 47.6.4.1 Definition 47.6.4.2 Different Multimaster Modes 47.6.5 Slave Mode 47.6.5.1 Definition 47.6.5.2 Programming Slave Mode 47.6.5.3 Receiving Data 47.6.5.4 Data Transfer 47.6.5.5 Using the DMA Controller (DMAC) in Slave Mode 47.6.5.6 SMBus Mode 47.6.5.7 High-Speed Slave Mode 47.6.5.8 Alternative Command 47.6.5.9 Asynchronous Partial Wakeup (SleepWalking) 47.6.5.10 Slave Read Write Flowcharts 47.6.5.11 FIFOs 47.6.6 TWIHS Comparison Function on Received Character 47.6.7 Register Write Protection 47.7 Two-wire Interface High Speed (TWIHS) User Interface 47.7.1 TWIHS Control Register 47.7.2 TWIHS Control Register (FIFO_ENABLED) 47.7.3 TWIHS Master Mode Register 47.7.4 TWIHS Slave Mode Register 47.7.5 TWIHS Internal Address Register 47.7.6 TWIHS Clock Waveform Generator Register 47.7.7 TWIHS Status Register 47.7.8 TWIHS Status Register (FIFO_ENABLED) 47.7.9 TWIHS SMBus Timing Register 47.7.10 TWIHS Alternative Command Register 47.7.11 TWIHS Filter Register 47.7.12 TWIHS Interrupt Enable Register 47.7.13 TWIHS Interrupt Disable Register 47.7.14 TWIHS Interrupt Mask Register 47.7.15 TWIHS Receive Holding Register 47.7.16 TWIHS Receive Holding Register (FIFO_ENABLED) 47.7.17 TWIHS SleepWalking Matching Register 47.7.18 TWIHS Transmit Holding Register 47.7.19 TWIHS Transmit Holding Register (FIFO_ENABLED) 47.7.20 TWIHS FIFO Mode Register 47.7.21 TWIHS FIFO Level Register 47.7.22 TWIHS FIFO Status Register 47.7.23 TWIHS FIFO Interrupt Enable Register 47.7.24 TWIHS FIFO Interrupt Disable Register 47.7.25 TWIHS FIFO Interrupt Mask Register 47.7.26 TWIHS Write Protection Mode Register 47.7.27 TWIHS Write Protection Status Register 48. Flexible Serial Communication Controller (FLEXCOM) 48.1 Description 48.2 Embedded Characteristics 48.2.1 USART/UART Characteristics 48.2.2 SPI Characteristics 48.2.3 TWI/SMBus Characteristics 48.3 Block Diagram 48.4 I/O Lines Description 48.5 Product Dependencies 48.5.1 I/O Lines 48.5.2 Power Management 48.5.3 Interrupt Sources 48.6 Register Accesses 48.7 USART Functional Description 48.7.1 Baud Rate Generator 48.7.1.1 Baud Rate in Asynchronous Mode 48.7.1.2 Fractional Baud Rate in Asynchronous Mode 48.7.1.3 Baud Rate in Synchronous Mode or SPI Mode 48.7.1.4 Baud Rate in ISO 7816 Mode 48.7.2 Receiver and Transmitter Control 48.7.3 Synchronous and Asynchronous Modes 48.7.3.1 Transmitter Operations 48.7.3.2 Manchester Encoder 48.7.3.3 Asynchronous Receiver 48.7.3.4 Manchester Decoder 48.7.3.5 Radio Interface: Manchester Encoded USART Application 48.7.3.6 Synchronous Receiver 48.7.3.7 Receiver Operations 48.7.3.8 Parity 48.7.3.9 Multidrop Mode 48.7.3.10 Transmitter Timeguard 48.7.3.11 Receiver Timeout 48.7.3.12 Framing Error 48.7.3.13 Transmit Break 48.7.3.14 Receive Break 48.7.3.15 Hardware Handshaking 48.7.4 ISO7816 Mode 48.7.4.1 ISO7816 Mode Overview 48.7.4.2 Protocol T = 0 48.7.4.3 Protocol T = 1 48.7.5 IrDA Mode 48.7.5.1 IrDA Modulation 48.7.5.2 IrDA Baud Rate 48.7.5.3 IrDA Demodulator 48.7.6 RS485 Mode 48.7.7 USART Comparison Function on Received Character 48.7.8 SPI Mode 48.7.8.1 Modes of Operation 48.7.8.2 Bit Rate 48.7.8.3 Data Transfer 48.7.8.4 Receiver and Transmitter Control 48.7.8.5 Character Transmission 48.7.8.6 Character Reception 48.7.8.7 Receiver Timeout 48.7.9 LIN Mode 48.7.9.1 Modes of Operation 48.7.9.2 Baud Rate Configuration 48.7.9.3 Receiver and Transmitter Control 48.7.9.4 Character Transmission 48.7.9.5 Character Reception 48.7.9.6 Header Transmission (Master Node Configuration) 48.7.9.7 Header Reception (Slave Node Configuration) 48.7.9.8 Slave Node Synchronization 48.7.9.9 Identifier Parity 48.7.9.10 Node Action 48.7.9.11 Response Data Length 48.7.9.12 Checksum 48.7.9.13 Frame Slot Mode 48.7.9.14 LIN Errors 48.7.9.15 LIN Frame Handling 48.7.9.16 LIN Frame Handling with the DMAC 48.7.9.17 Wakeup Request 48.7.9.18 Bus Idle Timeout 48.7.10 Test Modes 48.7.10.1 Normal Mode 48.7.10.2 Automatic Echo Mode 48.7.10.3 Local Loopback Mode 48.7.10.4 Remote Loopback Mode 48.7.11 USART FIFOs 48.7.11.1 Overview 48.7.11.2 Sending Data with FIFO Enabled 48.7.11.3 Receiving Data with FIFO Enabled 48.7.11.4 Clearing/Flushing FIFOs 48.7.11.5 TXEMPTY, TXRDY and RXRDY Behavior 48.7.11.6 USART Single Data Mode 48.7.11.7 USART Multiple Data Mode 48.7.11.8 Transmit FIFO Lock 48.7.11.9 FIFO Pointer Error 48.7.11.10 FIFO Thresholds 48.7.11.11 FIFO Flags 48.7.12 USART Register Write Protection 48.8 SPI Functional Description 48.8.1 Modes of Operation 48.8.2 Data Transfer 48.8.3 Master Mode Operations 48.8.3.1 Master Mode Block Diagram 48.8.3.2 Master Mode Flowchart 48.8.3.3 Clock Generation 48.8.3.4 Transfer Delays 48.8.3.5 Peripheral Selection 48.8.3.6 SPI Direct Access Memory Controller (DMAC) 48.8.3.7 Peripheral Chip Select Decoding 48.8.3.8 Peripheral Deselection without DMA 48.8.3.9 Peripheral Deselection with DMA 48.8.3.10 Mode Fault Detection 48.8.4 SPI Slave Mode 48.8.5 SPI Comparison Function on Received Character 48.8.6 SPI Asynchronous and Partial Wakeup (SleepWalking) 48.8.7 SPI FIFOs 48.8.7.1 Overview 48.8.7.2 Sending Data with FIFO Enabled 48.8.7.3 Receiving Data with FIFO Enabled 48.8.7.4 Clearing/Flushing FIFOs 48.8.7.5 TXEMPTY, TDRE and RDRF Behavior 48.8.7.6 SPI Single Data Mode 48.8.7.7 SPI Multiple Data Mode 48.8.7.8 FIFO Pointer Error 48.8.7.9 FIFO Thresholds 48.8.7.10 FIFO Flags 48.8.8 SPI Register Write Protection 48.9 TWI Functional Description 48.9.1 Transfer Format 48.9.2 Modes of Operation 48.9.3 Master Mode 48.9.3.1 Definition 48.9.3.2 Programming Master Mode 48.9.3.3 Transfer Speed/Bit Rate 48.9.3.4 Master Transmitter Mode 48.9.3.5 Master Receiver Mode 48.9.3.6 Internal Address 48.9.3.7 Repeated Start 48.9.3.8 Bus Clear Command 48.9.3.9 SMBus Mode 48.9.3.10 SMBus Quick Command (Master Mode Only) 48.9.3.11 Alternative Command 48.9.3.12 Handling Errors in Alternative Command 48.9.3.13 Read/Write Flowcharts 48.9.4 Multi-Master Mode 48.9.4.1 Definition 48.9.4.2 Different Multi-Master Modes 48.9.5 Slave Mode 48.9.5.1 Definition 48.9.5.2 Programming Slave Mode 48.9.5.3 Receiving Data 48.9.5.4 Data Transfer 48.9.5.5 High-Speed Slave Mode 48.9.5.6 Alternative Command 48.9.5.7 TWI Asynchronous and Partial Wakeup (SleepWalking) 48.9.5.8 Slave Read/Write Flowcharts 48.9.6 TWI FIFOs 48.9.6.1 Overview 48.9.6.2 Sending Data with FIFO Enabled 48.9.6.3 Receiving Data with FIFO Enabled 48.9.6.4 Sending/Receiving with FIFO Enabled in Slave Mode 48.9.6.5 Clearing/Flushing FIFOs 48.9.6.6 TXRDY and RXRDY Behavior 48.9.6.7 TWI Single Data Mode 48.9.6.8 TWI Multiple Data Mode 48.9.6.9 Transmit FIFO Lock 48.9.6.10 FIFO Pointer Error 48.9.6.11 FIFO Thresholds 48.9.6.12 FIFO Flags 48.9.7 TWI Comparison Function on Received Character 48.9.8 TWI Register Write Protection 48.10 Flexible Serial Communication Unit (FLEXCOM) User Interface 48.10.1 FLEXCOM Mode Register 48.10.2 FLEXCOM Transmit Holding Register 48.10.3 FLEXCOM Receive Holding Register 48.10.4 USART Control Register 48.10.5 USART Control Register (SPI_MODE) 48.10.6 USART Mode Register 48.10.7 USART Mode Register (SPI_MODE) 48.10.8 USART Interrupt Enable Register 48.10.9 USART Interrupt Enable Register (SPI_MODE) 48.10.10 USART Interrupt Enable Register (LIN_MODE) 48.10.11 USART Interrupt Disable Register 48.10.12 USART Interrupt Disable Register (SPI_MODE) 48.10.13 USART Interrupt Disable Register (LIN_MODE) 48.10.14 USART Interrupt Mask Register 48.10.15 USART Interrupt Mask Register (SPI_MODE) 48.10.16 USART Interrupt Mask Register (LIN_MODE) 48.10.17 USART Channel Status Register 48.10.18 USART Channel Status Register (SPI_MODE) 48.10.19 USART Channel Status Register (LIN_MODE) 48.10.20 USART Receive Holding Register 48.10.21 USART Receive Holding Register (FIFO Multi Data) 48.10.22 USART Transmit Holding Register 48.10.23 USART Transmit Holding Register (FIFO Multi Data) 48.10.24 USART Baud Rate Generator Register 48.10.25 USART Receiver Timeout Register 48.10.26 USART Transmitter Timeguard Register 48.10.27 USART FI DI RATIO Register 48.10.28 USART Number of Errors Register 48.10.29 USART IrDA FILTER Register 48.10.30 USART Manchester Configuration Register 48.10.31 USART LIN Mode Register 48.10.32 USART LIN Identifier Register 48.10.33 USART LIN Baud Rate Register 48.10.34 USART Comparison Register 48.10.35 USART FIFO Mode Register 48.10.36 USART FIFO Level Register 48.10.37 USART FIFO Interrupt Enable Register 48.10.38 USART FIFO Interrupt Disable Register 48.10.39 USART FIFO Interrupt Mask Register 48.10.40 USART FIFO Event Status Register 48.10.41 USART Write Protection Mode Register 48.10.42 USART Write Protection Status Register 48.10.43 SPI Control Register 48.10.44 SPI Mode Register 48.10.45 SPI Receive Data Register 48.10.46 SPI Receive Data Register (FIFO Multiple Data, 8-bit) 48.10.47 SPI Receive Data Register (FIFO Multiple Data, 16-bit) 48.10.48 SPI Transmit Data Register 48.10.49 SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit) 48.10.50 SPI Status Register 48.10.51 SPI Interrupt Enable Register 48.10.52 SPI Interrupt Disable Register 48.10.53 SPI Interrupt Mask Register 48.10.54 SPI Chip Select Register 48.10.55 SPI FIFO Mode Register 48.10.56 SPI FIFO Level Register 48.10.57 SPI Comparison Register 48.10.58 SPI Write Protection Mode Register 48.10.59 SPI Write Protection Status Register 48.10.60 TWI Control Register 48.10.61 TWI Control Register (FIFO_ENABLED) 48.10.62 TWI Master Mode Register 48.10.63 TWI Slave Mode Register 48.10.64 TWI Internal Address Register 48.10.65 TWI Clock Waveform Generator Register 48.10.66 TWI Status Register 48.10.67 TWI Status Register (FIFO ENABLED) 48.10.68 TWI Interrupt Enable Register 48.10.69 TWI Interrupt Disable Register 48.10.70 TWI Interrupt Mask Register 48.10.71 TWI Receive Holding Register 48.10.72 TWI Receive Holding Register (FIFO Enabled) 48.10.73 TWI Transmit Holding Register 48.10.74 TWI Transmit Holding Register (FIFO Enabled) 48.10.75 TWI SMBus Timing Register 48.10.76 TWI Alternative Command Register 48.10.77 TWI Filter Register 48.10.78 TWI SleepWalking Matching Register 48.10.79 TWI FIFO Mode Register 48.10.80 TWI FIFO Level Register 48.10.81 TWI FIFO Status Register 48.10.82 TWI FIFO Interrupt Enable Register 48.10.83 TWI FIFO Interrupt Disable Register 48.10.84 TWI FIFO Interrupt Mask Register 48.10.85 TWI Write Protection Mode Register 48.10.86 TWI Write Protection Status Register 49. Universal Asynchronous Receiver Transmitter (UART) 49.1 Description 49.2 Embedded Characteristics 49.3 Block Diagram 49.4 Product Dependencies 49.4.1 I/O Lines 49.4.2 Power Management 49.4.3 Interrupt Sources 49.5 Functional Description 49.5.1 Baud Rate Generator 49.5.2 Receiver 49.5.2.1 Receiver Reset, Enable and Disable 49.5.2.2 Start Detection and Data Sampling 49.5.2.3 Receiver Ready 49.5.2.4 Receiver Overrun 49.5.2.5 Parity Error 49.5.2.6 Receiver Framing Error 49.5.2.7 Receiver Digital Filter 49.5.2.8 Receiver Timeout 49.5.3 Transmitter 49.5.3.1 Transmitter Reset, Enable and Disable 49.5.3.2 Transmit Format 49.5.3.3 Transmitter Control 49.5.4 DMA Support 49.5.5 Comparison Function on Received Character 49.5.6 Asynchronous and Partial Wakeup (SleepWalking) 49.5.7 Register Write Protection 49.5.8 Test Modes 49.6 Universal Asynchronous Receiver Transmitter (UART) User Interface 49.6.1 UART Control Register 49.6.2 UART Mode Register 49.6.3 UART Interrupt Enable Register 49.6.4 UART Interrupt Disable Register 49.6.5 UART Interrupt Mask Register 49.6.6 UART Status Register 49.6.7 UART Receiver Holding Register 49.6.8 UART Transmit Holding Register 49.6.9 UART Baud Rate Generator Register 49.6.10 UART Comparison Register 49.6.11 UART Receiver Timeout Register 49.6.12 UART Write Protection Mode Register 50. Serial Peripheral Interface (SPI) 50.1 Description 50.2 Embedded Characteristics 50.3 Block Diagram 50.4 Application Block Diagram 50.5 Signal Description 50.6 Product Dependencies 50.6.1 I/O Lines 50.6.2 Power Management 50.6.3 Interrupt 50.6.4 Direct Memory Access Controller (DMAC) 50.7 Functional Description 50.7.1 Modes of Operation 50.7.2 Data Transfer 50.7.3 Master Mode Operations 50.7.3.1 Master Mode Block Diagram 50.7.3.2 Master Mode Flow Diagram 50.7.3.3 Clock Generation 50.7.3.4 Transfer Delays 50.7.3.5 Peripheral Selection 50.7.3.6 SPI Direct Access Memory Controller (DMAC) 50.7.3.7 Peripheral Chip Select Decoding 50.7.3.8 Peripheral Deselection without DMA 50.7.3.9 Peripheral Deselection with DMA 50.7.3.10 Mode Fault Detection 50.7.4 SPI Slave Mode 50.7.5 SPI Comparison Function on Received Character 50.7.6 SPI Asynchronous and Partial Wakeup (SleepWalking) 50.7.7 FIFOs 50.7.7.1 Overview 50.7.7.2 Sending Data with FIFO Enabled 50.7.7.3 Receiving Data with FIFO Enabled 50.7.7.4 Clearing/Flushing FIFOs 50.7.7.5 TXEMPTY, TDRE and RDRF Behavior 50.7.7.6 Single Data Mode 50.7.7.7 Multiple Data Mode 50.7.7.8 FIFO Pointer Error 50.7.7.9 FIFO Thresholds 50.7.7.10 FIFO Flags 50.7.8 Register Write Protection 50.8 Serial Peripheral Interface (SPI) User Interface 50.8.1 SPI Control Register 50.8.2 SPI Mode Register 50.8.3 SPI Receive Data Register 50.8.4 SPI Receive Data Register (FIFO Multiple Data, 8-bit) 50.8.5 SPI Receive Data Register (FIFO Multiple Data, 16-bit) 50.8.6 SPI Transmit Data Register 50.8.7 SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit) 50.8.8 SPI Status Register 50.8.9 SPI Interrupt Enable Register 50.8.10 SPI Interrupt Disable Register 50.8.11 SPI Interrupt Mask Register 50.8.12 SPI Chip Select Register 50.8.13 SPI FIFO Mode Register 50.8.14 SPI FIFO Level Register 50.8.15 SPI Comparison Register 50.8.16 SPI Write Protection Mode Register 50.8.17 SPI Write Protection Status Register 51. Quad Serial Peripheral Interface (QSPI) 51.1 Description 51.2 Embedded Characteristics 51.3 Block Diagram 51.4 Signal Description 51.5 Product Dependencies 51.5.1 I/O Lines 51.5.2 Power Management 51.5.3 Interrupt Sources 51.5.4 Direct Memory Access Controller (DMA) 51.6 Functional Description 51.6.1 Serial Clock Baud Rate 51.6.2 Serial Clock Phase and Polarity 51.6.3 Transfer Delays 51.6.4 QSPI SPI Mode 51.6.4.1 SPI Mode Operations 51.6.4.2 SPI Mode Block Diagram 51.6.4.3 SPI Mode Flow Diagram 51.6.4.4 Peripheral Deselection without DMA 51.6.4.5 Peripheral Deselection with DMA 51.6.5 QSPI Serial Memory Mode 51.6.5.1 Instruction Frame 51.6.5.2 Instruction Frame Transmission 51.6.5.3 Read Memory Transfer 51.6.5.4 Continuous Read Mode 51.6.5.5 Instruction Frame Transmission Examples 51.6.6 Scrambling/Unscrambling Function 51.6.7 Register Write Protection 51.7 Quad Serial Peripheral Interface (QSPI) User Interface 51.7.1 QSPI Control Register 51.7.2 QSPI Mode Register 51.7.3 QSPI Receive Data Register 51.7.4 QSPI Transmit Data Register 51.7.5 QSPI Status Register 51.7.6 QSPI Interrupt Enable Register 51.7.7 QSPI Interrupt Disable Register 51.7.8 QSPI Interrupt Mask Register 51.7.9 QSPI Serial Clock Register 51.7.10 QSPI Instruction Address Register 51.7.11 QSPI Instruction Code Register 51.7.12 QSPI Instruction Frame Register 51.7.13 QSPI Scrambling Mode Register 51.7.14 QSPI Scrambling Key Register 51.7.15 QSPI Write Protection Mode Register 51.7.16 QSPI Write Protection Status Register 52. Secure Digital MultiMedia Card Controller (SDMMC) 52.1 Description 52.2 Embedded Characteristics 52.3 Embedded Features for SDMMC0 and SDMMC1 52.4 Reference Documents 52.5 Block Diagram 52.6 Application Block Diagram 52.7 Pin Name List 52.8 Product Dependencies 52.8.1 I/O Lines 52.8.2 Power Management 52.8.3 Interrupt Sources 52.9 SD/SDIO Operating Mode 52.10 e.MMC Operating Mode 52.10.1 Boot Operation Mode 52.10.1.1 Boot Procedure, Processor Mode 52.10.1.2 Boot Procedure, SDMA Mode 52.10.1.3 Boot Procedure, ADMA Mode 52.11 SDR104 / HS200 Tuning 52.11.1 DLL and Sampling Point 52.11.2 Retuning Method 52.11.2.1 SDMMC Tuning Sequence 52.12 I/O Calibration 52.13 Secure Digital MultiMedia Card Controller (SDMMC) User Interface 52.13.1 SDMMC SDMA System Address / Argument 2 Register 52.13.2 SDMMC Block Size Register 52.13.3 SDMMC Block Count Register 52.13.4 SDMMC Argument 1 Register 52.13.5 SDMMC Transfer Mode Register 52.13.6 SDMMC Command Register 52.13.7 SDMMC Response Register 52.13.8 SDMMC Buffer Data Port Register 52.13.9 SDMMC Present State Register 52.13.10 SDMMC Host Control 1 Register (SD_SDIO) 52.13.11 SDMMC Host Control 1 Register (e.MMC) 52.13.12 SDMMC Power Control Register 52.13.13 SDMMC Block Gap Control Register (SD_SDIO) 52.13.14 SDMMC Block Gap Control Register (e.MMC) 52.13.15 SDMMC Wakeup Control Register (SD_SDIO) 52.13.16 SDMMC Clock Control Register 52.13.17 SDMMC Timeout Control Register 52.13.18 SDMMC Software Reset Register 52.13.19 SDMMC Normal Interrupt Status Register (SD_SDIO) 52.13.20 SDMMC Normal Interrupt Status Register (e.MMC) 52.13.21 SDMMC Error Interrupt Status Register (SD_SDIO) 52.13.22 SDMMC Error Interrupt Status Register (e.MMC) 52.13.23 SDMMC Normal Interrupt Status Enable Register (SD_SDIO) 52.13.24 SDMMC Normal Interrupt Status Enable Register (e.MMC) 52.13.25 SDMMC Error Interrupt Status Enable Register (SD_SDIO) 52.13.26 SDMMC Error Interrupt Status Enable Register (e.MMC) 52.13.27 SDMMC Normal Interrupt Signal Enable Register (SD_SDIO) 52.13.28 SDMMC Normal Interrupt Signal Enable Register (e.MMC) 52.13.29 SDMMC Error Interrupt Signal Enable Register (SD_SDIO) 52.13.30 SDMMC Error Interrupt Signal Enable Register (e.MMC) 52.13.31 SDMMC Auto CMD Error Status Register 52.13.32 SDMMC Host Control 2 Register (SD_SDIO) 52.13.33 SDMMC Host Control 2 Register (e.MMC) 52.13.34 SDMMC Capabilities 0 Register 52.13.35 SDMMC Capabilities 1 Register 52.13.36 SDMMC Maximum Current Capabilities Register 52.13.37 SDMMC Force Event Register for Auto CMD Error Status 52.13.38 SDMMC Force Event Register for Error Interrupt Status 52.13.39 SDMMC ADMA Error Status Register 52.13.40 SDMMC ADMA System Address Register 52.13.41 SDMMC Preset Value Register 52.13.42 SDMMC Slot Interrupt Status Register 52.13.43 SDMMC Host Controller Version Register 52.13.44 SDMMC Additional Present State Register 52.13.45 SDMMC e.MMC Control 1 Register 52.13.46 SDMMC e.MMC Control 2 Register 52.13.47 SDMMC AHB Control Register 52.13.48 SDMMC Clock Control 2 Register 52.13.49 SDMMC Retuning Control 1 Register 52.13.50 SDMMC Retuning Control 2 Register 52.13.51 SDMMC Retuning Counter Value Register 52.13.52 SDMMC Retuning Interrupt Status Enable Register 52.13.53 SDMMC Retuning Interrupt Signal Enable Register 52.13.54 SDMMC Retuning Interrupt Status Register 52.13.55 SDMMC Retuning Status Slots Register 52.13.56 SDMMC Tuning Control Register 52.13.57 SDMMC Capabilities Control Register 52.13.58 SDMMC Calibration Control Register 53. Image Sensor Controller (ISC) 53.1 Description 53.2 Embedded Characteristics 53.3 Block Diagram and Use Cases 53.3.1 Image Sensor Controller Functional Diagrams 53.3.2 Image Sensor Controller Clock Domain Diagram 53.3.3 Image Sensor Controller Typical Use Cases 53.4 Product Dependencies 53.4.1 I/O Lines 53.4.2 Power Management 53.4.3 Interrupt Sources 53.5 Functional Description 53.5.1 ISC Clock Management 53.5.1.1 Software Requirement 53.5.2 Parallel Interface Timing Description 53.5.3 BT.601/656/1120 Embedded Timing Synchronization Operation 53.5.4 Parallel Interface External Sensor Connections 53.5.4.1 YCbCr, 10-bit CCIR656 with Embedded Synchronization 53.5.4.2 YCbCr, 8-bit CCIR656 with Embedded Synchronization 53.5.4.3 RAW Bayer Parallel Interface 53.5.4.4 Monochrome Parallel Interface 53.5.5 Parallel Front End (PFE) Module 53.5.5.1 Update the ISC Profile 53.5.5.2 Software Requirements 53.5.6 White Balance (WB) Module 53.5.7 Color Filter Array (CFA) Interpolation Module 53.5.7.1 Frame Size Requirement when Edge Interpolation is Off, ISC_CFA_CFG.EITPOL Cleared 53.5.7.2 Frame Size Requirement when Edge Interpolation is On, ISC_CFA_CFG.EITPOL Set 53.5.7.3 Bayer Mode and Edge Interpolation Description 53.5.8 Color Correction (CC) Module 53.5.9 Gamma Curve (GAM) Module 53.5.10 Color Space Conversion (CSC) Module 53.5.11 Contrast and Brightness 53.5.12 4:4:4 To 4:2:2 Chrominance Horizontal Subsampler (SUB422) Module 53.5.13 4:2:2 To 4:2:0 Chrominance Vertical Subsampler (SUB420) Module 53.5.14 Rounding, Limiting and Packing (RLP) Module 53.5.15 DMA Interface 53.5.15.1 Descriptor Memory Address Mapping 53.5.15.2 Descriptor Memory Mapping 53.5.15.3 Example: Memory Mapping for 16-bit Packed, DMA Interface IMODE = 1 at ISC_DAD0.AD0 Location 53.5.15.4 Example: Memory Mapping for 12-bit YC420SP, DMA Interface IMODE = 5 53.5.15.5 Example: Memory Mapping for 12-bit YC420P, DMA Interface IMODE = 6 53.5.16 Histogram Module 53.6 Image Sensor Controller (ISC) User Interface 53.6.1 ISC Control Enable Register 0 53.6.2 ISC Control Disable Register 0 53.6.3 ISC Control Status Register 0 53.6.4 ISC Parallel Front End Configuration 0 Register 53.6.5 ISC Parallel Front End Configuration 1 Register 53.6.6 ISC Parallel Front End Configuration 2 Register 53.6.7 ISC Clock Enable Register 53.6.8 ISC Clock Disable Register 53.6.9 ISC Clock Status Register 53.6.10 ISC Clock Configuration Register 53.6.11 ISC Interrupt Enable Register 53.6.12 ISC Interrupt Disable Register 53.6.13 ISC Interrupt Mask Register 53.6.14 ISC Interrupt Status Register 53.6.15 ISC White Balance Control Register 53.6.16 ISC White Balance Configuration Register 53.6.17 ISC White Balance Offset for R, GR Register 53.6.18 ISC White Balance Offset for B and GB Register 53.6.19 ISC White Balance Gain for R, GR Register 53.6.20 ISC White Balance Gain for B, GB Register 53.6.21 ISC Color Filter Array Control Register 53.6.22 ISC Color Filter Array Configuration Register 53.6.23 ISC Color Correction Control Register 53.6.24 ISC Color Correction RR RG Register 53.6.25 ISC Color Correction RB OR Register 53.6.26 ISC Color Correction GR GG Register 53.6.27 ISC Color Correction GB OG Register 53.6.28 ISC Color Correction BR BG Register 53.6.29 ISC Color Correction BB OB Register 53.6.30 ISC Gamma Correction Control Register 53.6.31 ISC Gamma Correction Blue Entry Register 53.6.32 ISC Gamma Correction Green Entry Register 53.6.33 ISC Gamma Correction Red Entry Register 53.6.34 ISC Color Space Conversion Control Register 53.6.35 ISC Color Space Conversion YR YG Register 53.6.36 ISC Color Space Conversion YB OY Register 53.6.37 ISC Color Space Conversion CBR CBG Register 53.6.38 ISC Color Space Conversion CBB OCB Register 53.6.39 ISC Color Space Conversion CRR CRG Register 53.6.40 ISC Color Space Conversion CRB OCR Register 53.6.41 ISC Contrast And Brightness Control Register 53.6.42 ISC Contrast And Brightness Configuration Register 53.6.43 ISC Contrast And Brightness, Brightness Register 53.6.44 ISC Contrast And Brightness, Contrast Register 53.6.45 ISC Subsampling 4:4:4 to 4:2:2 Control Register 53.6.46 ISC Subsampling 4:4:4 to 4:2:2 Configuration Register 53.6.47 ISC Subsampling 4:2:2 to 4:2:0 Control Register 53.6.48 ISC Rounding, Limiting and Packing Configuration Register 53.6.49 ISC Histogram Control Register 53.6.50 ISC Histogram Configuration Register 53.6.51 ISC DMA Configuration Register 53.6.52 ISC DMA Control Register 53.6.53 ISC DMA Descriptor Address Register 53.6.54 ISC DMA Address 0 Register 53.6.55 ISC DMA Stride 0 Register 53.6.56 ISC DMA Address 1 Register 53.6.57 ISC DMA Stride 1 Register 53.6.58 ISC DMA Address 2 Register 53.6.59 ISC DMA Stride 2 Register 53.6.60 ISC Histogram Entry 54. Controller Area Network (MCAN) 54.1 Description 54.2 Embedded Characteristics 54.3 Block Diagram 54.4 Product Dependencies 54.4.1 I/O Lines 54.4.2 Power Management 54.4.3 Interrupt Sources 54.4.4 Address Configuration 54.5 Functional Description 54.5.1 Operating Modes 54.5.1.1 Software Initialization 54.5.1.2 Normal Operation 54.5.1.3 CAN FD Operation 54.5.1.4 Transmitter Delay Compensation 54.5.1.5 Restricted Operation Mode 54.5.1.6 Bus Monitoring Mode 54.5.1.7 Disabled Automatic Retransmission 54.5.1.8 Power-down (Sleep Mode) 54.5.1.9 Test Modes 54.5.2 Timestamp Generation 54.5.3 Timeout Counter 54.5.4 Rx Handling 54.5.4.1 Acceptance Filtering 54.5.4.2 Rx FIFOs 54.5.4.3 Dedicated Rx Buffers 54.5.4.4 Debug on CAN Support 54.5.5 Tx Handling 54.5.5.1 Transmit Pause 54.5.5.2 Dedicated Tx Buffers 54.5.5.3 Tx FIFO 54.5.5.4 Tx Queue 54.5.5.5 Mixed Dedicated Tx Buffers / Tx FIFO 54.5.5.6 Mixed Dedicated Tx Buffers / Tx Queue 54.5.5.7 Transmit Cancellation 54.5.5.8 Tx Event Handling 54.5.6 FIFO Acknowledge Handling 54.5.7 Message RAM 54.5.7.1 Message RAM Configuration 54.5.7.2 Rx Buffer and FIFO Element 54.5.7.3 Tx Buffer Element 54.5.7.4 Tx Event FIFO Element 54.5.7.5 Standard Message ID Filter Element 54.5.7.6 Extended Message ID Filter Element 54.5.8 Hardware Reset Description 54.5.9 Access to Reserved Register Addresses 54.6 Controller Area Network (MCAN) User Interface 54.6.1 MCAN Core Release Register 54.6.2 MCAN Endian Register 54.6.3 MCAN Customer Register 54.6.4 MCAN Data Bit Timing and Prescaler Register 54.6.5 MCAN Test Register 54.6.6 MCAN RAM Watchdog Register 54.6.7 MCAN CC Control Register 54.6.8 MCAN Nominal Bit Timing and Prescaler Register 54.6.9 MCAN Timestamp Counter Configuration Register 54.6.10 MCAN Timestamp Counter Value Register 54.6.11 MCAN Timeout Counter Configuration Register 54.6.12 MCAN Timeout Counter Value Register 54.6.13 MCAN Error Counter Register 54.6.14 MCAN Protocol Status Register 54.6.15 MCAN Transmitter Delay Compensation Register 54.6.16 MCAN Interrupt Register 54.6.17 MCAN Interrupt Enable Register 54.6.18 MCAN Interrupt Line Select Register 54.6.19 MCAN Interrupt Line Enable 54.6.20 MCAN Global Filter Configuration 54.6.21 MCAN Standard ID Filter Configuration 54.6.22 MCAN Extended ID Filter Configuration 54.6.23 MCAN Extended ID AND Mask 54.6.24 MCAN High Priority Message Status 54.6.25 MCAN New Data 1 54.6.26 MCAN New Data 2 54.6.27 MCAN Receive FIFO 0 Configuration 54.6.28 MCAN Receive FIFO 0 Status 54.6.29 MCAN Receive FIFO 0 Acknowledge 54.6.30 MCAN Receive Buffer Configuration 54.6.31 MCAN Receive FIFO 1 Configuration 54.6.32 MCAN Receive FIFO 1 Status 54.6.33 MCAN Receive FIFO 1 Acknowledge 54.6.34 MCAN Receive Buffer / FIFO Element Size Configuration 54.6.35 MCAN Tx Buffer Configuration 54.6.36 MCAN Tx FIFO/Queue Status 54.6.37 MCAN Tx Buffer Element Size Configuration 54.6.38 MCAN Transmit Buffer Request Pending 54.6.39 MCAN Transmit Buffer Add Request 54.6.40 MCAN Transmit Buffer Cancellation Request 54.6.41 MCAN Transmit Buffer Transmission Occurred 54.6.42 MCAN Transmit Buffer Cancellation Finished 54.6.43 MCAN Transmit Buffer Transmission Interrupt Enable 54.6.44 MCAN Transmit Buffer Cancellation Finished Interrupt Enable 54.6.45 MCAN Transmit Event FIFO Configuration 54.6.46 MCAN Tx Event FIFO Status 54.6.47 MCAN Tx Event FIFO Acknowledge 55. Timer Counter (TC) 55.1 Description 55.2 Embedded Characteristics 55.3 Block Diagram 55.4 Pin List 55.5 Product Dependencies 55.5.1 I/O Lines 55.5.2 Power Management 55.5.3 Interrupt Sources 55.5.4 Synchronization Inputs from PWM 55.5.5 Fault Output 55.6 Functional Description 55.6.1 Description 55.6.2 32-bit Counter 55.6.3 Clock Selection 55.6.4 Clock Control 55.6.5 Operating Modes 55.6.6 Trigger 55.6.7 Capture Mode 55.6.8 Capture Registers A and B 55.6.9 Transfer with DMAC in Capture Mode 55.6.10 Trigger Conditions 55.6.11 Waveform Mode 55.6.12 Waveform Selection 55.6.12.1 WAVSEL = 00 55.6.12.2 WAVSEL = 10 55.6.12.3 WAVSEL = 01 55.6.12.4 WAVSEL = 11 55.6.13 External Event/Trigger Conditions 55.6.14 Synchronization with PWM 55.6.15 Output Controller 55.6.16 Quadrature Decoder 55.6.16.1 Description 55.6.16.2 Input Preprocessing 55.6.16.3 Direction Status and Change Detection 55.6.16.4 Position and Rotation Measurement 55.6.16.5 Speed Measurement 55.6.16.6 Detecting a Missing Index Pulse 55.6.16.7 Detecting Contamination/Dust at Rotary Encoder Low Speed 55.6.16.8 Missing Pulse Detection and Autocorrection 55.6.17 2-bit Gray Up/Down Counter for Stepper Motor 55.6.18 Fault Mode 55.6.19 Register Write Protection 55.7 Timer Counter (TC) User Interface 55.7.1 TC Channel Control Register 55.7.2 TC Channel Mode Register: Capture Mode 55.7.3 TC Channel Mode Register: Waveform Mode 55.7.4 TC Stepper Motor Mode Register 55.7.5 TC Register AB 55.7.6 TC Counter Value Register 55.7.7 TC Register A 55.7.8 TC Register B 55.7.9 TC Register C 55.7.10 TC Interrupt Status Register 55.7.11 TC Interrupt Enable Register 55.7.12 TC Interrupt Disable Register 55.7.13 TC Interrupt Mask Register 55.7.14 TC Extended Mode Register 55.7.15 TC Block Control Register 55.7.16 TC Block Mode Register 55.7.17 TC QDEC Interrupt Enable Register 55.7.18 TC QDEC Interrupt Disable Register 55.7.19 TC QDEC Interrupt Mask Register 55.7.20 TC QDEC Interrupt Status Register 55.7.21 TC Fault Mode Register 55.7.22 TC Write Protection Mode Register 56. Pulse Density Modulation Interface Controller (PDMIC) 56.1 Description 56.2 Embedded Characteristics 56.3 Block Diagram 56.4 Signal Description 56.5 Product Dependencies 56.5.1 I/O Lines 56.5.2 Power Management 56.5.3 Interrupt Sources 56.6 Functional Description 56.6.1 PDM Interface 56.6.1.1 Description 56.6.1.2 Startup Sequence 56.6.2 Digital Signal Processing (Digital Filter) 56.6.2.1 Description 56.6.2.2 Decimation Filter 56.6.2.3 Droop Compensation 56.6.2.4 Low Pass Filter 56.6.2.5 High Pass Filter 56.6.2.6 Gain and Offset Compensation 56.6.3 Conversion Results 56.6.4 Register Write Protection 56.7 Pulse Density Modulation Interface Controller (PDMIC) User Interface 56.7.1 PDMIC Control Register 56.7.2 PDMIC Mode Register 56.7.3 PDMIC Converted Data Register 56.7.4 PDMIC Interrupt Enable Register 56.7.5 PDMIC Interrupt Disable Register 56.7.6 PDMIC Interrupt Mask Register 56.7.7 PDMIC Interrupt Status Register 56.7.8 PDMIC DSP Configuration Register 0 56.7.9 PDMIC DSP Configuration Register 1 56.7.10 PDMIC Write Protection Mode Register 56.7.11 PDMIC Write Protection Status Register 57. Pulse Width Modulation Controller (PWM) 57.1 Description 57.2 Embedded Characteristics 57.3 Block Diagram 57.4 I/O Lines Description 57.5 Product Dependencies 57.5.1 I/O Lines 57.5.2 Power Management 57.5.3 Interrupt Sources 57.5.4 Fault Inputs 57.6 Functional Description 57.6.1 PWM Clock Generator 57.6.2 PWM Channel 57.6.2.1 Channel Block Diagram 57.6.2.2 Comparator 57.6.2.3 Trigger Selection for Timer Counter 57.6.2.4 2-bit Gray Up/Down Counter for Stepper Motor 57.6.2.5 Dead-Time Generator 57.6.2.6 Output Override 57.6.2.7 Fault Protection 57.6.2.8 Spread Spectrum Counter 57.6.2.9 Synchronous Channels 57.6.2.10 Update Time for Double-Buffering Registers 57.6.3 PWM Comparison Units 57.6.4 PWM Event Lines 57.6.5 PWM External Trigger Mode 57.6.5.1 External PWM Reset Mode 57.6.5.2 External PWM Start Mode 57.6.5.3 Cycle-By-Cycle Duty Mode 57.6.5.4 Leading-Edge Blanking (LEB) 57.6.6 PWM Controller Operations 57.6.6.1 Initialization 57.6.6.2 Source Clock Selection Criteria 57.6.6.3 Changing the Duty-Cycle, the Period and the Dead-Times 57.6.6.4 Changing the Update Period of Synchronous Channels 57.6.6.5 Changing the Comparison Value and the Comparison Configuration 57.6.6.6 Interrupt Sources 57.6.7 Register Write Protection 57.7 Pulse Width Modulation Controller (PWM) User Interface 57.7.1 PWM Clock Register 57.7.2 PWM Enable Register 57.7.3 PWM Disable Register 57.7.4 PWM Status Register 57.7.5 PWM Interrupt Enable Register 1 57.7.6 PWM Interrupt Disable Register 1 57.7.7 PWM Interrupt Mask Register 1 57.7.8 PWM Interrupt Status Register 1 57.7.9 PWM Sync Channels Mode Register 57.7.10 PWM DMA Register 57.7.11 PWM Sync Channels Update Control Register 57.7.12 PWM Sync Channels Update Period Register 57.7.13 PWM Sync Channels Update Period Update Register 57.7.14 PWM Interrupt Enable Register 2 57.7.15 PWM Interrupt Disable Register 2 57.7.16 PWM Interrupt Mask Register 2 57.7.17 PWM Interrupt Status Register 2 57.7.18 PWM Output Override Value Register 57.7.19 PWM Output Selection Register 57.7.20 PWM Output Selection Set Register 57.7.21 PWM Output Selection Clear Register 57.7.22 PWM Output Selection Set Update Register 57.7.23 PWM Output Selection Clear Update Register 57.7.24 PWM Fault Mode Register 57.7.25 PWM Fault Status Register 57.7.26 PWM Fault Clear Register 57.7.27 PWM Fault Protection Value Register 1 57.7.28 PWM Fault Protection Enable Register 57.7.29 PWM Event Line x Register 57.7.30 PWM Spread Spectrum Register 57.7.31 PWM Spread Spectrum Update Register 57.7.32 PWM Stepper Motor Mode Register 57.7.33 PWM Fault Protection Value Register 2 57.7.34 PWM Write Protection Control Register 57.7.35 PWM Write Protection Status Register 57.7.36 PWM Comparison x Value Register 57.7.37 PWM Comparison x Value Update Register 57.7.38 PWM Comparison x Mode Register 57.7.39 PWM Comparison x Mode Update Register 57.7.40 PWM Channel Mode Register 57.7.41 PWM Channel Duty Cycle Register 57.7.42 PWM Channel Duty Cycle Update Register 57.7.43 PWM Channel Period Register 57.7.44 PWM Channel Period Update Register 57.7.45 PWM Channel Counter Register 57.7.46 PWM Channel Dead Time Register 57.7.47 PWM Channel Dead Time Update Register 57.7.48 PWM Channel Mode Update Register 57.7.49 PWM External Trigger Register 57.7.50 PWM Leading-Edge Blanking Register 58. Secure Fuse Controller (SFC) 58.1 Description 58.2 Embedded Characteristics 58.3 Block Diagram 58.4 Functional Description 58.4.1 Accessing the SFC 58.4.2 Fuse Partitioning 58.4.3 Fuse Integrity Checking 58.4.4 Fuse Integrity Live Checking 58.4.5 Fuse Access 58.4.5.1 Fuse Reading 58.4.5.2 Fuse Programming 58.4.5.3 Fuse Masking 58.4.6 Fuse Functions 58.5 Secure Fuse Controller (SFC) User Interface 58.5.1 SFC Key Register 58.5.2 SFC Mode Register 58.5.3 SFC Interrupt Enable Register 58.5.4 SFC Interrupt Disable Register 58.5.5 SFC Interrupt Mask Register 58.5.6 SFC Status Register 58.5.7 SFC Data Register x 59. Integrity Check Monitor (ICM) 59.1 Description 59.2 Embedded Characteristics 59.3 Block Diagram 59.4 Product Dependencies 59.4.1 Power Management 59.4.2 Interrupt Sources 59.5 Functional Description 59.5.1 Overview 59.5.2 ICM Region Descriptor Structure 59.5.2.1 ICM Region Start Address Structure Member 59.5.2.2 ICM Region Configuration Structure Member 59.5.2.3 ICM Region Control Structure Member 59.5.2.4 ICM Region Next Address Structure Member 59.5.3 ICM Hash Area 59.5.3.1 Message Digest Example 59.5.4 Using ICM as SHA Engine 59.5.4.1 Settings for Simple SHA Calculation 59.5.4.2 Processing Period 59.5.5 ICM Automatic Monitoring Mode 59.5.6 Programming the ICM 59.5.7 Security Features 59.6 Integrity Check Monitor (ICM) User Interface 59.6.1 ICM Configuration Register 59.6.2 ICM Control Register 59.6.3 ICM Status Register 59.6.4 ICM Interrupt Enable Register 59.6.5 ICM Interrupt Disable Register 59.6.6 ICM Interrupt Mask Register 59.6.7 ICM Interrupt Status Register 59.6.8 ICM Undefined Access Status Register 59.6.9 ICM Descriptor Area Start Address Register 59.6.10 ICM Hash Area Start Address Register 59.6.11 ICM User Initial Hash Value Register 60. Advanced Encryption Standard Bridge (AESB) 60.1 Embedded Characteristics 60.2 Product Dependencies 60.2.1 Power Management 60.2.2 Interrupt 60.3 Functional Description 60.3.1 Operating Modes 60.3.2 Double Input Buffer 60.3.3 Start Modes 60.3.3.1 Manual Mode 60.3.3.2 Auto Mode 60.3.4 Last Output Data Mode 60.3.5 Manual and Auto Modes 60.3.5.1 If AESB_MR.LOD = 0 60.3.5.2 If AESB_MR.LOD = 1 60.3.6 Automatic Bridge Mode 60.3.6.1 Description 60.3.6.2 Configuration 60.3.7 Security Features 60.3.7.1 Unspecified Register Access Detection 60.4 Advanced Encryption Standard Bridge (AESB) User Interface 60.4.1 AESB Control Register 60.4.2 AESB Mode Register 60.4.3 AESB Interrupt Enable Register 60.4.4 AESB Interrupt Disable Register 60.4.5 AESB Interrupt Mask Register 60.4.6 AESB Interrupt Status Register 60.4.7 AESB Key Word Register x 60.4.8 AESB Input Data Register x 60.4.9 AESB Output Data Register x 60.4.10 AESB Initialization Vector Register x 61. Advanced Encryption Standard (AES) 61.1 Description 61.2 Embedded Characteristics 61.3 Product Dependencies 61.3.1 Power Management 61.3.2 Interrupt Sources 61.4 Functional Description 61.4.1 AES Register Endianness 61.4.2 Operating Modes 61.4.3 Double Input Buffer 61.4.4 Start Modes 61.4.4.1 Manual Mode 61.4.4.2 Auto Mode 61.4.4.3 DMA Mode 61.4.5 Last Output Data Mode 61.4.5.1 Manual and Auto Modes 61.4.5.2 DMA Mode 61.4.6 Galois/Counter Mode (GCM) 61.4.6.1 Description 61.4.6.2 Key Writing and Automatic Hash Subkey Calculation 61.4.6.3 GCM Processing 61.4.7 XEX-based Tweaked-codebook Mode (XTS) 61.4.7.1 XTS Processing Procedure 61.4.8 Automatic Padding Mode 61.4.8.1 IPSEC Padding 61.4.8.2 SSL Padding 61.4.8.3 Flags 61.4.9 Secure Protocol Layers Improved Performances 61.4.9.1 Cipher Mode 61.4.9.2 Decipher Mode 61.4.9.3 Encapsulating Security Payload (ESP) IPSec Examples 61.4.10 Security Features 61.4.10.1 Unspecified Register Access Detection 61.5 Advanced Encryption Standard (AES) User Interface 61.5.1 AES Control Register 61.5.2 AES Mode Register 61.5.3 AES Interrupt Enable Register 61.5.4 AES Interrupt Disable Register 61.5.5 AES Interrupt Mask Register 61.5.6 AES Interrupt Status Register 61.5.7 AES Key Word Register x 61.5.8 AES Input Data Register x 61.5.9 AES Output Data Register x 61.5.10 AES Initialization Vector Register x 61.5.11 AES Additional Authenticated Data Length Register 61.5.12 AES Plaintext/Ciphertext Length Register 61.5.13 AES GCM Intermediate Hash Word Register x 61.5.14 AES GCM Authentication Tag Word Register x 61.5.15 AES GCM Encryption Counter Value Register 61.5.16 AES GCM H Word Register x 61.5.17 AES Extended Mode Register 61.5.18 AES Byte Counter Register 61.5.19 AES Tweak Word Register x 61.5.20 AES Alpha Word Register x 62. Secure Hash Algorithm (SHA) 62.1 Description 62.2 Embedded Characteristics 62.3 Product Dependencies 62.3.1 Power Management 62.3.2 Interrupt Sources 62.4 Functional Description 62.4.1 SHA Algorithm 62.4.2 HMAC Algorithm 62.4.3 Processing Period 62.4.4 Double Input Buffer 62.4.5 Internal Registers for Initial Hash Value or Expected Hash Result 62.4.6 Automatic Padding 62.4.7 Automatic Check 62.4.8 Protocol Layers Improved Performances 62.4.9 Start Modes 62.4.9.1 Manual Mode 62.4.9.2 Auto Mode 62.4.9.3 DMA Mode 62.4.9.4 SHA Register Endianness 62.4.10 Security Features 62.4.10.1 Unspecified Register Access Detection 62.5 Secure Hash Algorithm (SHA) User Interface 62.5.1 SHA Control Register 62.5.2 SHA Mode Register 62.5.3 SHA Interrupt Enable Register 62.5.4 SHA Interrupt Disable Register 62.5.5 SHA Interrupt Mask Register 62.5.6 SHA Interrupt Status Register 62.5.7 SHA Message Size Register 62.5.8 SHA Bytes Count Register 62.5.9 SHA Input Data x Register 62.5.10 SHA Input/Output Data Register x 63. Triple Data Encryption Standard (TDES) 63.1 Description 63.2 Embedded Characteristics 63.3 Product Dependencies 63.3.1 Power Management 63.3.2 Interrupt Sources 63.4 Functional Description 63.4.1 Operating Modes 63.4.2 Start Modes 63.4.2.1 Manual Mode 63.4.2.2 Auto Mode 63.4.2.3 DMA Mode 63.4.3 Last Output Data Mode 63.4.3.1 Manual and Auto Modes 63.4.3.2 DMA Mode 63.4.4 Security Features 63.4.4.1 Unspecified Register Access Detection 63.5 Triple Data Encryption Standard (TDES) User Interface 63.5.1 TDES Control Register 63.5.2 TDES Mode Register 63.5.3 TDES Interrupt Enable Register 63.5.4 TDES Interrupt Disable Register 63.5.5 TDES Interrupt Mask Register 63.5.6 TDES Interrupt Status Register 63.5.7 TDES Key 1 Word Register x 63.5.8 TDES Key 2 Word Register x 63.5.9 TDES Key 3 Word Register x 63.5.10 TDES Input Data Register x 63.5.11 TDES Output Data Register x 63.5.12 TDES Initialization Vector Register x 63.5.13 TDES XTEA Rounds Register 64. True Random Number Generator (TRNG) 64.1 Description 64.2 Embedded Characteristics 64.3 Block Diagram 64.4 Product Dependencies 64.4.1 Power Management 64.4.2 Interrupt Sources 64.5 Functional Description 64.6 True Random Number Generator (TRNG) User Interface 64.6.1 TRNG Control Register 64.6.2 TRNG Interrupt Enable Register 64.6.3 TRNG Interrupt Disable Register 64.6.4 TRNG Interrupt Mask Register 64.6.5 TRNG Interrupt Status Register 64.6.6 TRNG Output Data Register 65. Security Module (SECUMOD) 65.1 Description 65.2 Embedded Characteristics 65.3 Block Diagram 65.3.1 I/O Lines Description 65.4 Product Dependencies 65.4.1 Interrupt Sources 65.5 Functional Description 65.5.1 Memory Mapping 65.5.2 Scrambling Keys 65.5.3 Internal Random Number Generator (IRNG) 65.5.4 Protection Mechanisms 65.5.4.1 PIO Backup Controller 65.5.4.2 JTAG Prevention 65.5.5 Erasing Secure Memories 65.5.5.1 BUSRAM4KB Erase Sequence 65.5.5.2 BUREG256b Erase Sequence 65.5.6 Operating Modes 65.5.6.1 Protection Unit 65.5.7 Activation or Deactivation of Protections 65.5.8 Powerup Reset 65.6 Security Module (SECUMOD) User Interface 65.6.1 SECUMOD Control Register 65.6.2 SECUMOD System Status Register 65.6.3 SECUMOD Status Register 65.6.4 SECUMOD Status Clear Register 65.6.5 SECUMOD RAM Access Ready Register 65.6.6 SECUMOD PIO Backup Register x 65.6.7 SECUMOD JTAG Protection Control Register 65.6.8 SECUMOD Scrambling Key Register 65.6.9 SECUMOD RAM Access Rights Register 65.6.10 SECUMOD RAM Access Rights Status Register 65.6.11 SECUMOD Backup Mode Protection Register 65.6.12 SECUMOD Normal Mode Protection Register 65.6.13 SECUMOD Normal Interrupt Enable Protection Register 65.6.14 SECUMOD Normal Interrupt Disable Protection Register 65.6.15 SECUMOD Normal Interrupt Mask Protection Register 65.6.16 SECUMOD Wakeup Register 66. Analog-to-Digital Converter (ADC) 66.1 Description 66.2 Embedded Characteristics 66.3 Block Diagram 66.4 Signal Description 66.5 Product Dependencies 66.5.1 Power Management 66.5.2 Interrupt Sources 66.5.3 I/O Lines 66.5.4 Hardware Triggers 66.5.5 Fault Output 66.6 Functional Description 66.6.1 Analog-to-Digital Conversion 66.6.2 ADC Clock 66.6.3 ADC Reference Voltage 66.6.4 Conversion Resolution 66.6.5 Conversion Results 66.6.6 Conversion Results Format 66.6.7 Conversion Triggers 66.6.8 Sleep Mode and Conversion Sequencer 66.6.9 Comparison Window 66.6.10 Differential and Single-ended Input Modes 66.6.10.1 Input-output Transfer Functions 66.6.11 ADC Timings 66.6.12 Last Channel Specific Measurement Trigger 66.6.13 Enhanced Resolution Mode and Digital Averaging Function 66.6.13.1 Enhanced Resolution Mode 66.6.13.2 Averaging Function versus Trigger Events 66.6.14 Automatic Error Correction 66.6.15 Touchscreen 66.6.15.1 Touchscreen Mode 66.6.15.2 4-wire Resistive Touchscreen Principles 66.6.15.3 4-wire Position Measurement Method 66.6.15.4 4-wire Pressure Measurement Method 66.6.15.5 5-wire Resistive Touchscreen Principles 66.6.15.6 5-wire Position Measurement Method 66.6.15.7 Sequence and Noise Filtering 66.6.15.8 Measured Values, Registers and Flags 66.6.15.9 Pen Detect Method 66.6.16 Asynchronous and Partial Wakeup (SleepWalking) 66.6.17 Buffer Structure 66.6.17.1 Classic ADC Channels Only (Touchscreen Disabled) 66.6.17.2 Touchscreen Channels Only 66.6.17.3 Interleaved Channels 66.6.17.4 Pen Detection Status 66.6.18 Fault Event 66.6.19 Register Write Protection 66.7 Analog-to-Digital (ADC) User Interface 66.7.1 ADC Control Register 66.7.2 ADC Mode Register 66.7.3 ADC Channel Sequence 1 Register 66.7.4 ADC Channel Sequence 2 Register 66.7.5 ADC Channel Enable Register 66.7.6 ADC Channel Disable Register 66.7.7 ADC Channel Status Register 66.7.8 ADC Last Converted Data Register 66.7.9 ADC Interrupt Enable Register 66.7.10 ADC Interrupt Disable Register 66.7.11 ADC Interrupt Mask Register 66.7.12 ADC Interrupt Status Register 66.7.13 ADC Last Channel Trigger Mode Register 66.7.14 ADC Last Channel Compare Window Register 66.7.15 ADC Overrun Status Register 66.7.16 ADC Extended Mode Register 66.7.17 ADC Compare Window Register 66.7.18 ADC Channel Offset Register 66.7.19 ADC Channel Data Register 66.7.20 ADC Analog Control Register 66.7.21 ADC Touchscreen Mode Register 66.7.22 ADC Touchscreen X Position Register 66.7.23 ADC Touchscreen Y Position Register 66.7.24 ADC Touchscreen Pressure Register 66.7.25 ADC Trigger Register 66.7.26 ADC Correction Values Register 66.7.27 ADC Channel Error Correction Register 66.7.28 ADC Touchscreen Correction Values Register 66.7.29 ADC Write Protection Mode Register 66.7.30 ADC Write Protection Status Register 67. Electrical Characteristics 67.1 Absolute Maximum Ratings 67.2 DC Characteristics 67.3 Power Consumption in Low-power Modes 67.3.1 Backup Mode 67.3.2 Backup Mode with DDR in Self-refresh 67.3.3 Ultra Low-power (ULP) Mode 67.3.3.1 ULP0 Mode 67.3.3.2 ULP1 Mode 67.3.4 Idle Mode 67.3.5 Low-power Mode Summary Table 67.3.6 Low Power Consumption Versus Modes 67.4 Clock Characteristics 67.4.1 Processor Clock Characteristics 67.4.2 Master Clock Characteristics 67.5 Oscillator Characteristics 67.5.1 Main Oscillator Characteristics 67.5.1.1 Recommended Crystal Characteristics 67.5.1.2 XIN Clock Characteristics 67.5.2 32.768 kHz Crystal Oscillator Characteristics 67.5.3 64 kHz RC Oscillator Characteristics 67.6 PLL Characteristics 67.7 USB HS Characteristics 67.7.1 Electrical Characteristics 67.7.2 Dynamic Power Consumption 67.8 PTC Characteristics 67.9 ADC Characteristics 67.9.1 ADC Power Supply 67.9.1.1 Power Supply Characteristics 67.9.2 External Reference Voltage 67.9.3 ADC Timings 67.9.4 ADC Transfer Function 67.9.4.1 Differential Mode (12-bit mode) 67.9.4.2 Single-ended Mode (12-bit mode) 67.9.4.3 Example of LSB Computation 67.9.4.4 Gain and Offset Errors 67.9.5 ADC Electrical Characteristics 67.9.6 ADC Channel Input Impedance 67.10 Analog Comparator Characteristics 67.11 SMC Timings 67.11.1 Timing Conditions 67.11.2 SMC IOSET1 Timing Extraction 67.11.2.1 SMC IOSET1 Read Timings 67.11.2.2 SMC IOSET1 Write Timings 67.11.3 SMC IOSET2 Timing Extraction 67.11.3.1 SMC IOSET2 Read Timings 67.11.3.2 SMC IOSET2 Write Timings 67.12 FLEXCOM Timings 67.12.1 FLEXCOM USART in Asynchronous Modes 67.12.2 FLEXCOM SPI Timings 67.12.2.1 Timing Conditions 67.12.2.2 Timing Extraction 67.12.3 FLEXCOM TWI Timings 67.13 USART in Asynchronous Modes 67.14 SPI Timings 67.14.1 Maximum SPI Frequency 67.14.2 Timing Conditions 67.14.3 Timing Extraction 67.15 TWI Timings 67.16 QSPI Timings 67.16.1 Maximum QSPI Frequency 67.16.2 Timing Conditions 67.16.3 Timing Extraction 67.17 MPDDRC Timings 67.17.1 Board Design Constraints 67.17.2 DDR2-SDRAM 67.17.3 LPDDR1-SDRAM 67.17.4 LPDDR2/LPDDR3-SDRAM 67.17.5 DDR3/DDR3L-SDRAM 67.18 SSC Timings 67.18.1 Timing Conditions 67.18.2 Timing Extraction 67.19 PDMIC Timings 67.19.1 Timing Conditions 67.19.2 Timing Extraction 67.20 I2SC Timings 67.20.1 Timing Conditions 67.20.2 Timing Extraction 67.21 ISC Timings 67.21.1 Timing Conditions 67.21.2 Timing Extraction 67.22 SDMMC Timings 67.23 GMAC Timings 67.23.1 Timing Conditions 67.23.2 Timing Constraints 67.23.2.1 Ethernet MAC MII Mode 67.23.2.2 Ethernet MAC RMII Mode 68. Mechanical Characteristics 68.1 289-ball LFBGA Mechanical Characteristics 69. Schematic Checklist 69.1 Power Supply 69.2 Power-On Reset 69.3 Clock, Oscillator and PLL 69.3.1 How to Define the Oscillator Load Capacitance 69.4 ICE and JTAG 69.5 Reset and Test 69.6 Shutdown/Wakeup Logic 69.7 Parallel Input/Output (PIO) 69.8 Analog-to-Digital Converter (ADC) 69.9 External Bus Interface (EBI) 69.10 USB High-Speed Host Port (UHPHS) / USB High-Speed Device Port (UDPHS) 69.11 Boot Program Hardware Constraints 69.12 Layout and Design Constraints 69.12.1 General Considerations 69.12.2 Considerations for High-Speed Differential Interfaces 69.12.3 DDR Layout and Design Considerations 69.12.4 e.MMC routing 69.12.5 USB Trace Routing Guidelines 69.12.6 QSPI Pull-up Resistors 69.12.7 Considerations for PTC Interface 70. Marking 71. Ordering Information 72. Errata 72.1 GMAC Timestamps and PTP packets 72.2 SDMMC software ‘Reset for All’ Command 72.3 FLEXCOM SMBUS 72.4 TWI/TWIHS Clear Command 72.5 SSC TD Output 72.6 I2SC First Sent Data 72.7 Quad I/O Serial Peripheral Interface (QSPI) 72.8 Master/Processor Clock Prescaler 72.9 Master CAN-FD Controller (MCAN) 72.10 MCAN Interrupt MCAN_IR.MRAF 72.11 MCAN Bus Integration State 72.12 MCAN Message RAM/RAM Arbiter 72.13 MCAN Frame Receiving 72.14 MCAN Edge Filtering 72.15 MCAN_NBTP.NTSEG2 Configuration 72.16 MCAN DAR Mode 72.17 MCAN Tx FIFO Message 72.18 MCAN High Priority Message (HPM) 72.19 ROM Code: Using JTAG IOSET 4 73. Revision History 73.1 Rev. A - 03/2018 The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV ASIA/PACIFIC
