Datasheet SAMA5D3 (Microchip) - 1813
| Manufacturer | Microchip |
| Description | Low-Power Arm Cortex -A5 Processor-Based MPU, 536 MHz, FPU, Gigabit Ethernet with IEEE 1588 plus 10/100 Ethernet, Dual CAN, AES, SHA |
| Pages / Page | 1818 / 1813 — SAMA5D3 SERIES Doc. Rev. 11121B Change. Request. Ref. Comments. … |
| File Format / Size | PDF / 30.1 Mb |
| Document Language | English |
SAMA5D3 SERIES Doc. Rev. 11121B Change. Request. Ref. Comments. Introduction:
Model Line for this Datasheet
Text Version of Document
SAMA5D3 SERIES Doc. Rev.
11121B Change
Request
Ref. Comments
Introduction:
Section 8.1 “Chip Identification”, updated Chip ID: “0x8A5C07C1” -> “0x8A5C07C2”. rfo “Description” , added a cross-reference to Table 1-1 “SAMA5D3 Device Differences” in the last paragraph. rfo ™ ® Replaced “Cortex ” references with “Cortex ” in “Description” and further on in the entire document. rfo Removed “AT91SAM” from the document title.
Standard Boot Strategies:
Section 11.4.4.1 NAND Flash Boot: NAND Flash Detection, added the eccBitReq field description in “NAND
Flash Specific Header Detection” . 8796 SFR:
Added a row for SFR_UTMICKTRIM register (offset value “0x30”) in Table 16-1 "Register Mapping" and the
corresponding Table 16.3.5 "UTMI Clock Trimming Register". 8683 External Memories:
Section 28.1.4 Product Dependencies, updated LPDDR2 Mode data in Table 28-2 “DDR2 I/O Lines Usage vs rfo
Operating Modes” (DDR_WE, DDR_RAS -DDR_CAS, and DDR_A[13.0]).
Section 28.1.5.2 2x16-bit LPDDR2, added references on CAx LP-DDR2 signals and Table 28-3 “CAx LPDDR2
Signal Connection”.
USART:
Added a paragraph on IRDA_FILTER programming criteria in Section 45.7.5.3 “IrDA Demodulator” and in the
corresponding field description in Section 45.8.20 “USART IrDA FILTER Register”. 8508 Section 45.8.18 “USART FI DI RATIO Register”, expanded FI_DI_RATIO field to 16 bits in the register table. 8643 FUSE:
Section 50.2 “Embedded Characteristics”, added references on FUSE bits. 8785 Added Section 50.2.1 “FUSE Bit Mapping” and Section 50.2.2 “Special Functions”.
Electrical Characteristics:
Section 54.6 “12 MHz RC Oscillator Characteristics”, updated the IDDON value in Table 54-12. rfo Section 54.7 “32 kHz Oscillator Characteristics”, added a row on PON in Table 54-13.
Section 54.11 “12-Bit ADC Characteristics”, updated data in:
-Table 54-22 “Analog Power Supply Characteristics”
-Table 54-23 “Channel Conversion Time and ADC Clock”
-Table 54-24 “External Voltage Reference Input”
-Table 54-25 “INL, DNL, 12-bit mode, VDDANA 2.4V to 3.6V supply voltage conditions”
-Table 54-26 “Gain Error, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage conditions”
-Table 54-27 “Error offset with or without calibration, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage
conditions”
-Table 54-28 “Dynamic Performance Characteristics in Single ended and 12 bits mode (1)”; and
-Table 54-29 “Dynamic Performance Characteristics in Differential and 12 bits mode(1)”
Added Section 54.15 “MPDDRC Timings” rfo Section 54.16 “SSC Timings”, updated PIXCLK frequency maximum value and fixed transmitter parameter
data for SSC7 in Table 54-47 “SSC Timings with 3.3V Peripheral supply” and Table 54-48 “SSC Timing with
1V8 Peripheral supply” rfo DS60001609B-page 1814 2020 Microchip Technology Inc.
11121B Change
Request
Ref. Comments
Introduction:
Section 8.1 “Chip Identification”, updated Chip ID: “0x8A5C07C1” -> “0x8A5C07C2”. rfo “Description” , added a cross-reference to Table 1-1 “SAMA5D3 Device Differences” in the last paragraph. rfo ™ ® Replaced “Cortex ” references with “Cortex ” in “Description” and further on in the entire document. rfo Removed “AT91SAM” from the document title.
Standard Boot Strategies:
Section 11.4.4.1 NAND Flash Boot: NAND Flash Detection, added the eccBitReq field description in “NAND
Flash Specific Header Detection” . 8796 SFR:
Added a row for SFR_UTMICKTRIM register (offset value “0x30”) in Table 16-1 "Register Mapping" and the
corresponding Table 16.3.5 "UTMI Clock Trimming Register". 8683 External Memories:
Section 28.1.4 Product Dependencies, updated LPDDR2 Mode data in Table 28-2 “DDR2 I/O Lines Usage vs rfo
Operating Modes” (DDR_WE, DDR_RAS -DDR_CAS, and DDR_A[13.0]).
Section 28.1.5.2 2x16-bit LPDDR2, added references on CAx LP-DDR2 signals and Table 28-3 “CAx LPDDR2
Signal Connection”.
USART:
Added a paragraph on IRDA_FILTER programming criteria in Section 45.7.5.3 “IrDA Demodulator” and in the
corresponding field description in Section 45.8.20 “USART IrDA FILTER Register”. 8508 Section 45.8.18 “USART FI DI RATIO Register”, expanded FI_DI_RATIO field to 16 bits in the register table. 8643 FUSE:
Section 50.2 “Embedded Characteristics”, added references on FUSE bits. 8785 Added Section 50.2.1 “FUSE Bit Mapping” and Section 50.2.2 “Special Functions”.
Electrical Characteristics:
Section 54.6 “12 MHz RC Oscillator Characteristics”, updated the IDDON value in Table 54-12. rfo Section 54.7 “32 kHz Oscillator Characteristics”, added a row on PON in Table 54-13.
Section 54.11 “12-Bit ADC Characteristics”, updated data in:
-Table 54-22 “Analog Power Supply Characteristics”
-Table 54-23 “Channel Conversion Time and ADC Clock”
-Table 54-24 “External Voltage Reference Input”
-Table 54-25 “INL, DNL, 12-bit mode, VDDANA 2.4V to 3.6V supply voltage conditions”
-Table 54-26 “Gain Error, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage conditions”
-Table 54-27 “Error offset with or without calibration, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage
conditions”
-Table 54-28 “Dynamic Performance Characteristics in Single ended and 12 bits mode (1)”; and
-Table 54-29 “Dynamic Performance Characteristics in Differential and 12 bits mode(1)”
Added Section 54.15 “MPDDRC Timings” rfo Section 54.16 “SSC Timings”, updated PIXCLK frequency maximum value and fixed transmitter parameter
data for SSC7 in Table 54-47 “SSC Timings with 3.3V Peripheral supply” and Table 54-48 “SSC Timing with
1V8 Peripheral supply” rfo DS60001609B-page 1814 2020 Microchip Technology Inc.
