Datasheet PIC32MX1XX/2XX/5XX 64/100-PIN (Microchip)

PIC32MX1XX/2XX/5XX 64/100-PIN 32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog Operating Conditions
- Programmable reference with 32 voltage points • 2.3V to 3.6V, -40ºC to +105ºC (DC to 40 MHz),
Timers/Output Compare/Input Capture
-40ºC to +85ºC (DC to 50 MHz) • Five General Purpose Timers:
Core: 50 MHz/83 DMIPS MIPS32® M4K®
- Five 16-bit and up to two 32-bit Timers/Counters • MIPS16e® mode for up to 40% smaller code size • Five Output Compare (OC) modules • Code-efficient (C and Assembly) architecture • Five Input Capture (IC) modules • Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply • Peripheral Pin Select (PPS) to allow function remap
Clock Management
• Real-Time Clock and Calendar (RTCC) module • 0.9% internal oscillator
Communication Interfaces
• Programmable PLLs and oscil ator clock sources • USB 2.0-compliant Full-speed OTG controller • Fail-Safe Clock Monitor (FSCM) • Up to five UART modules (12.5 Mbps): • Independent Watchdog Timer - LIN 2.1 protocols and IrDA® support • Fast wake-up and start-up • Four 4-wire SPI modules (25 Mbps)
Power Management
• Two I2C modules (up to 1 Mbaud) with SMBus support • PPS to allow function remap • Low-power management modes (Sleep and Idle) • Parallel Master Port (PMP) with dual read/write buffers • Integrated Power-on Reset, Brown-out Reset, and High • Controller Area Network (CAN) 2.0B Compliant with Voltage Detect DeviceNet™ addressing support • 0.5 mA/MHz dynamic current (typical) • 44 μA IPD current (typical)
Direct Memory Access (DMA) Audio/Graphics/Touch HMI Features
• Four channels of hardware DMA with automatic data size detection • External graphics interface with up to 34 PMP pins • 32-bit Programmable Cyclic Redundancy Check (CRC) • Audio data communication: I2S, LJ, RJ, USB • Two additional channels dedicated to USB • Audio data control interface: SPI and I2C • Two additional channels dedicated to CAN • Audio data master clock: - Generation of fractional clock frequencies
Input/Output
- Can be synchronized with USB clock • 10 mA or 15 mA source/sink for standard VOH/VOL and - Can be tuned in run-time up to 22 mA for non-standard VOH1 • Charge Time Measurement Unit (CTMU): • 5V-tolerant pins - Supports mTouch
®
capacitive touch sensing • Selectable open drain, pull-ups, and pull-downs - Provides high-resolution time measurement (1 ns) • External interrupts on all I/O pins
Advanced Analog Features Class B Support
• ADC Module: • Class B Safety Library, IEC 60730 - 10-bit 1 Msps rate with one Sample and Hold (S&H) - Up to 48 analog inputs
Debugger Development Support
- Can operate during Sleep mode • In-circuit and in-application programming • Flexible and independent ADC trigger sources • 4-wire MIPS® Enhanced JTAG interface • On-chip temperature measurement capability • Unlimited program and six complex data breakpoints • Comparators: • IEEE 1149.2-compatible (JTAG) boundary scan - Three dual-input Comparator modules
Packages Type QFN TQFP TFBGA Pin Count
64 64 100 100 100
I/O Pins (up to)
53 53 85 85 85
Contact/Lead Pitch
0.50 mm 0.50 mm 0.40 mm 0.50 mm 0.65 mm
Dimensions
9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 7x7x1.2 mm  2014-2019 Microchip Technology Inc. DS60001290F-page 1 Document Outline 1.0 Device Overview FIGURE 1-1: PIC32MX1XX/2XX/5XX 64/100-pin Block Diagram Table 1-1: Pinout I/O Descriptions 2.0 Guidelines for Getting Started with 32-bit MCUs 2.1 Basic Connection Requirements 2.2 Decoupling Capacitors FIGURE 2-1: Recommended Minimum Connection 2.3 Capacitor on Internal Voltage Regulator (Vcap) 2.4 Master Clear (MCLR) Pin FIGURE 2-2: Example of MCLR Pin Connections 2.5 ICSP Pins 2.6 JTAG 2.7 External Oscillator Pins FIGURE 2-3: Suggested Oscillator Circuit Placement EXAMPLE 2-1: Crystal Load Capacitor Calculation FIGURE 2-4: Primary crystal oscillator circuit recommendations 2.8 Unused I/Os 2.9 Considerations When Interfacing to Remotely Powered Circuits FIGURE 2-5: PIC32 Non-5V Tolerant Circuit Example TABLE 2-1: Examples of digital/ Analog Isolators with optional level translation FIGURE 2-6: Digital/Analog Signal Isolation Circuits FIGURE 2-7: PIC32 5V Tolerant Pin Architecture Example 2.10 Typical Application Connection Examples FIGURE 2-8: Capacitive Touch Sensing With Graphics Application FIGURE 2-9: Audio Playback Application FIGURE 2-10: Low-cost Controllerless (LCC) Graphics Application With Projected Capacitive Touch 2.11 EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2) Suppression Considerations FIGURE 2-11: EMI/EMC/EFT Suppression Circuit 3.0 CPU 3.1 Features FIGURE 3-1: MIPS32® M4K® Processor Core Block Diagram 3.2 Architecture Overview Table 3-1: MIPS32® M4K® processor core High-Performance Integer Multiply/ Divide Unit Latencies and Repeat Rates Table 3-2: Coprocessor 0 Registers Table 3-3: MIPS32® M4K® processor core Exception Types 3.3 Power Management 3.4 EJTAG Debug Support 4.0 Memory Organization 4.1 Memory Layout FIGURE 4-1: Memory Map for Devices with 64 KB of Program Memory + 8 KB RAM FIGURE 4-2: Memory Map for Devices With 128 KB of Program Memory + 16 kb ram FIGURE 4-3: Memory Map for Devices With 256 KB of Program Memory + 32 kb ram FIGURE 4-4: Memory Map for Devices With 512 KB of Program Memory + 64 kb ram Table 4-1: SFR Memory Map 4.2 Special Function Register Maps TABLE 4-2: Bus Matrix Register Map 4.3 Control Registers Register 4-1: BMXCON: Bus Matrix Configuration Register Register 4-2: BMXDKPBA: Data RAM Kernel Program Base Address Register Register 4-3: BMXDUDBA: Data RAM User Data Base Address Register Register 4-4: BMXDUPBA: Data RAM User Program Base Address Register Register 4-5: BMXDRMSZ: Data RAM Size Register Register 4-6: BMXPUPBA: Program Flash (PFM) User Program Base Address Register Register 4-7: BMXPFMSZ: Program Flash (PFM) Size Register Register 4-8: BMXBOOTSZ: Boot Flash (IFM) Size Register 5.0 Interrupt Controller FIGURE 5-1: Interrupt Controller Module Block Diagram Table 5-1: Interrupt IRQ, Vector and Bit Location 5.1 Interrupts Control Registers TABLE 5-2: Interrupt Register Map Register 5-1: INTCON: Interrupt Control Register Register 5-2: INTSTAT: Interrupt Status Register Register 5-3: IPTMR: Interrupt Proximity Timer Register Register 5-4: IFSx: Interrupt Flag Status Register Register 5-5: IECx: Interrupt Enable Control Register Register 5-6: IPCx: Interrupt Priority Control Register 6.0 Flash Program Memory 6.1 Control Registers TABLE 6-1: Flash Controller Register Map Register 6-1: NVMCON: Programming Control Register Register 6-2: NVMKEY: Programming Unlock Register Register 6-3: NVMADDR: Flash Address Register Register 6-4: NVMDATA: Flash Program Data Register Register 6-5: NVMSRCADDR: Source Data Address Register 7.0 Resets FIGURE 7-1: System Reset Block Diagram 7.1 Control Registers Table 7-1: Reset SFR Summary Register 7-1: RCON: Reset Control Register Register 7-2: RSWRST: Software Reset Register 8.0 Oscillator Configuration FIGURE 8-1: PIC32MX1XX/2XX/5XX 64/100-pin Family Clock Diagram FIGURE 8-2: PIC32MX1XX/2XX/5XX PLL Block Diagram 8.1 Control Registers TABLE 8-1: Oscillator Configuration Register Map Register 8-1: OSCCON: Oscillator Control Register Register 8-2: OSCTUN: FRC Tuning Register Register 8-3: REFOCON: Reference Oscillator Control Register Register 8-4: REFOTRIM: Reference Oscillator Trim Register 9.0 Direct Memory Access (DMA) Controller FIGURE 9-1: DMA Block Diagram 9.1 Control Registers TABLE 9-1: DMA Global Register Map TABLE 9-2: DMA CRC Register Map TABLE 9-3: DMA Channel 0 THROUGH Channel 3 Register Map Register 9-1: DMACON: DMA Controller Control Register Register 9-2: DMASTAT: DMA Status Register Register 9-3: DMAADDR: DMA Address Register Register 9-4: DCRCCON: DMA CRC Control Register Register 9-5: DCRCDATA: DMA CRC Data Register Register 9-6: DCRCXOR: DMA CRCXOR Enable Register Register 9-7: DCHxCON: DMA Channel ‘x’ Control Register Register 9-8: DCHxECON: DMA Channel ‘x’ Event Control Register Register 9-9: DCHxINT: DMA Channel ‘x’ Interrupt Control Register Register 9-10: DCHxSSA: DMA Channel ‘x’ Source Start Address Register Register 9-11: DCHxDSA: DMA Channel ‘x’ Destination Start Address Register Register 9-12: DCHxSSIZ: DMA Channel ‘x’ Source Size Register Register 9-13: DCHxDSIZ: DMA Channel ‘x’ Destination Size Register Register 9-14: DCHxSPTR: DMA Channel ‘x’ Source Pointer Register Register 9-15: DCHxDPTR: DMA Channel ‘x’ Destination Pointer Register Register 9-16: DCHxCSIZ: DMA Channel ‘x’ Cell-Size Register Register 9-17: DCHxCPTR: DMA Channel ‘x’ Cell Pointer Register Register 9-18: DCHxDAT: DMA Channel ‘x’ Pattern Data Register 10.0 USB On-The-Go (OTG) FIGURE 10-1: PIC32MX1XX/2XX/5XX USB Interface Diagram 10.1 Control Registers TABLE 10-1: USB Register Map Register 10-1: U1OTGIR: USB OTG Interrupt Status Register Register 10-2: U1OTGIE: USB OTG Interrupt Enable Register Register 10-3: U1OTGSTAT: USB OTG Status Register Register 10-4: U1OTGCON: USB OTG Control Register Register 10-5: U1PWRC: USB Power Control Register Register 10-6: U1IR: USB Interrupt Register Register 10-7: U1IE: USB Interrupt Enable Register Register 10-8: U1EIR: USB Error Interrupt Status Register Register 10-9: U1EIE: USB Error Interrupt Enable Register Register 10-10: U1STAT: USB Status Register Register 10-11: U1CON: USB Control Register Register 10-12: U1ADDR: USB Address Register Register 10-13: U1FRML: USB Frame Number Low Register Register 10-14: U1FRMH: USB Frame Number High Register Register 10-15: U1TOK: USB Token Register Register 10-16: U1SOF: USB SOF Threshold Register Register 10-17: U1BDTP1: USB BDT Page 1 Register Register 10-18: U1BDTP2: USB BDT PAGE 2 Register Register 10-19: U1BDTP3: USB BDT PAGE 3 Register Register 10-20: U1CNFG1: USB Configuration 1 Register Register 10-21: U1EP0-U1EP15: USB Endpoint Control Register 11.0 I/O Ports FIGURE 11-1: Block Diagram of a Typical Multiplexed Port Structure 11.1 Parallel I/O (PIO) Ports 11.2 CLR, SET, and INV Registers 11.3 Peripheral Pin Select FIGURE 11-2: Remappable Input Example for U1RX TABLE 11-1: Input Pin Selection FIGURE 11-3: Example of Multiplexing of Remappable Output for RPA0 Table 11-2: Output Pin Selection 11.4 Control Registers TABLE 11-3: PORTA Register Map 100-pin devices Only TABLE 11-4: PORTB Register Map TABLE 11-5: PORTC Register Map for 100-pin Devices Only TABLE 11-6: PORTC Register Map for 64-pin Devices Only TABLE 11-7: PORTD Register Map for 100-pin Devices Only TABLE 11-8: PORTD Register Map for 64-pin Devices Only TABLE 11-9: PORTE Register Map for 100-pin Devices Only TABLE 11-10: PORTE Register Map for 64-pin Devices Only TABLE 11-11: PORTF Register Map for PIC32MX130F128L, PIC32MX150F256L, and PIC32MX170F512L Devices Only TABLE 11-12: PORTF Register Map for PIC32MX230F128L, PIC32MX530F128L, PIC32MX250F256L, PIC32MX550F256L, PIC32MX270F512L, and PIC32MX570F512L Devices Only TABLE 11-13: PORTF Register Map for PIC32MX120F064H, PIC32MX130F128H, PIC32MX150F256H, and PIC32MX170F512H Devices Only TABLE 11-14: PORTF Register Map for PIC32MX230F128H, PIC32MX530F128H, PIC32MX250F256H, PIC32MX550F256H, PIC32MX270F512H, and PIC32MX570F512H Devices Only TABLE 11-15: PORTG Register Map for 100-pin Devices Only TABLE 11-16: PORTG Register Map for 64-pin Devices Only Table 11-17: Peripheral Pin Select Input Register Map Table 11-18: Peripheral Pin Select Output Register Map Register 11-1: [pin name]R: Peripheral Pin Select Input Register Register 11-2: RPnR: Peripheral Pin Select Output Register Register 11-3: CNCONx: Change Notice control for PORTx Register (x = A – G) 12.0 Timer1 12.1 Additional Supported Features FIGURE 12-1: Timer1 Block Diagram 12.2 Control Registers TABLE 12-1: Timer1 Register Map Register 12-1: T1CON: Type A Timer Control Register 13.0 Timer2/3, Timer4/5 13.1 Additional Supported Features FIGURE 13-1: Timer2, 3, 4, 5 Block Diagram (16-bit) FIGURE 13-2: Timer2/3, 4/5 Block Diagram (32-bit)(1) 13.2 Control Registers TABLE 13-1: Timer2 THROUGH Timer5 Register Map Register 13-1: TxCON: Type B Timer ‘x’ Control Register (‘x’ = 2 through 5) 14.0 Watchdog Timer (WDT) Figure 14-1: Watchdog and Power-Up Timer Block Diagram TABLE 14-1: Watchdog Timer Register Map Register 14-1: WDTCON: Watchdog Timer Control Register 15.0 Input Capture FIGURE 15-1: Input Capture Block Diagram 15.1 Control Registers TABLE 15-1: Input Capture 1 THROUGH Input Capture 5 Register Map Register 15-1: ICxCON: Input Capture ‘x’ Control Register (‘x’ = 1 through 5) 16.0 Output Compare FIGURE 16-1: Output Compare Module Block Diagram 16.1 Control Registers TABLE 16-1: Output Compare 1 THROUGH Output Compare 5 Register Map Register 16-1: OCxCON: Output Compare ‘x’ Control Register (‘x’ = 1 through 5) 17.0 Serial Peripheral Interface (SPI) FIGURE 17-1: SPI Module Block Diagram 17.1 Control Registers Table 17-1: spi1 through SPI4 Register Map Register 17-1: SPIx CON: SPI Control Register Register 17-2: SPIxCON2: SPI Control Register 2 Register 17-3: SPIxSTAT: SPI Status Register 18.0 Inter-Integrated Circuit (I2C) FIGURE 18-1: I2C Block Diagram 18.1 Control Registers TABLE 18-1: I2C1 and I2C2 Register Map Register 18-1: I2CxCON: I2C ‘x’ Control Register (‘x’ = 1 and 2) Register 18-2: I2CxSTAT: I2C Status Register 19.0 Universal Asynchronous Receiver Transmitter (UART) FIGURE 19-1: UART Simplified Block Diagram 19.1 Control Registers TABLE 19-1: UART1 THROUGH UART5 Register Map Register 19-1: UxMODE: UARTx Mode Register Register 19-2: UxSTA: UARTx Status and Control Register 19.2 Timing Diagrams FIGURE 19-2: UART Reception FIGURE 19-3: Transmission (8-bit or 9-bit Data) 20.0 Parallel Master Port (PMP) FIGURE 20-1: PMP Module Pinout and Connections to External Devices 20.1 Control Registers TABLE 20-1: Parallel Master Port Register Map Register 20-1: PMCON: Parallel Port Control Register Register 20-2: PMMODE: Parallel Port Mode Register Register 20-3: PMADDR: Parallel Port Address Register Register 20-4: PMDOUT: Parallel Port Output Data Register Register 20-5: PMDIN: Parallel Port Input Data Register Register 20-6: PMAEN: Parallel Port Pin Enable Register Register 20-7: PMSTAT: Parallel Port Status Register (Slave modes only) Register 20-8: PMWADDR: Parallel Port Write Address Register Register 20-9: PMRADDR: Parallel Port Read Address Register Register 20-10: PMRDIN: Parallel Port Read Input Data Register 21.0 Real-Time Clock and Calendar (RTCC) FIGURE 21-1: RTCC Block Diagram 21.1 Control Registers TABLE 21-1: RTCC Register Map Register 21-1: RTCCON: RTC Control Register Register 21-2: RTCALRM: RTC ALARM Control Register Register 21-3: RTCTIME: RTC Time Value Register Register 21-4: RTCDATE: RTC Date Value Register Register 21-5: ALRMTIME: Alarm Time Value Register Register 21-6: ALRMDATE: Alarm Date Value Register 22.0 10-bit Analog-to-Digital Converter (ADC) FIGURE 22-1: ADC1 Module Block Diagram FIGURE 22-2: ADC Conversion Clock Period Block Diagram 22.1 Control Registers TABLE 22-1: ADC Register Map Register 22-1: AD1CON1: ADC Control Register 1 Register 22-2: AD1CON2: ADC Control Register 2 Register 22-3: AD1CON3: ADC Control Register 3 Register 22-4: AD1CHS: ADC Input Select Register Register 22-5: AD1CSSL: ADC Input Scan Select Register Register 22-6: AD1CSSL2: ADC Input Scan Select Register 2 23.0 Controller Area Network (CAN) FIGURE 23-1: PIC32 CAN Module Block Diagram 23.1 Control Registers TABLE 23-1: CAN1 Register Summary Register 23-1: C1CON: CAN Module Control Register Register 23-2: C1CFG: CAN Baud Rate Configuration Register Register 23-3: C1INT: CAN Interrupt Register Register 23-4: C1VEC: CAN Interrupt Code Register Register 23-5: C1TREC: CAN Transmit/Receive Error Count Register Register 23-6: C1FSTAT: CAN FIFO Status Register Register 23-7: C1RXOVF: CAN Receive FIFO Overflow Status Register Register 23-8: C1TMR: CAN Timer Register Register 23-9: C1RXMn: CAN Acceptance Filter Mask ‘n’ Register (n = 0, 1, 2 or 3) Register 23-10: C1FLTCON0: CAN Filter Control Register 0 Register 23-11: C1FLTCON1: CAN Filter Control Register 1 Register 23-12: C1FLTCON2: CAN Filter Control Register 2 Register 23-13: C1FLTCON3: CAN Filter Control Register 3 Register 23-14: C1RXFn: CAN Acceptance Filter ‘n’ Register (‘n’ = 0 through 15) Register 23-15: C1FIFOBA: CAN Message Buffer Base Address Register Register 23-16: C1FIFOCONn: CAN FIFO Control Register ‘n’ (‘n’ = 0 through 15) Register 23-17: C1FIFOINTn: CAN FIFO Interrupt Register ‘n’ (‘n’ = 0 through 15) Register 23-18: C1FIFOUAn: CAN FIFO User Address Register ‘n’ (‘n’ = 0 through 15) Register 23-19: C1FIFOCIn: CAN Module Message Index Register ‘n’ (‘n’ = 0 through 15) 24.0 Comparator FIGURE 24-1: Comparator Block Diagram 24.1 Control Registers TABLE 24-1: Comparator Register Map Register 24-1: CMxCON: Comparator Control Register Register 24-2: CMSTAT: Comparator Status Register 25.0 Comparator Voltage Reference (CVref) FIGURE 25-1: Comparator Voltage Reference Block Diagram 25.1 Control Registers TABLE 25-1: Comparator Voltage Reference Register Map Register 25-1: CVRCON: Comparator Voltage Reference Control Register 26.0 Charge Time Measurement Unit (CTMU) FIGURE 26-1: CTMU Block Diagram 26.1 Control Registers TABLE 26-1: CTMU Register Map Register 26-1: CTMUCON: CTMU Control Register 27.0 Power-Saving Features 27.1 Power Saving with CPU Running 27.2 CPU Halted Methods 27.3 Power-Saving Operation 27.4 Peripheral Module Disable Table 27-1: Peripheral Module Disable Bits and Locations TABLE 27-2: Peripheral Module Disable Register Summary 28.0 Special Features 28.1 Configuration Bits 28.2 Registers TABLE 28-1: DEVCFG: Device Configuration Word Summary TABLE 28-2: Device and Revision ID Summary Register 28-1: DEVCFG0: Device Configuration Word 0 Register 28-2: DEVCFG1: Device Configuration Word 1 Register 28-3: DEVCFG2: Device Configuration Word 2 Register 28-4: DEVCFG3: Device Configuration Word 3 Register 28-5: CFGCON: Configuration Control Register Register 28-6: DEVID: Device and Revision ID Register 28.3 On-Chip Voltage Regulator Figure 28-1: Connections for the On-Chip Regulator 28.4 Programming and Diagnostics Figure 28-2: Block Diagram of Programming, Debugging and Trace Ports 29.0 Instruction Set 30.0 Development Support 30.1 MPLAB X Integrated Development Environment Software 30.2 MPLAB XC Compilers 30.3 MPASM Assembler 30.4 MPLINK Object Linker/ MPLIB Object Librarian 30.5 MPLAB Assembler, Linker and Librarian for Various Device Families 30.6 MPLAB X SIM Software Simulator 30.7 MPLAB REAL ICE In-Circuit Emulator System 30.8 MPLAB ICD 3 In-Circuit Debugger System 30.9 PICkit 3 In-Circuit Debugger/ Programmer 30.10 MPLAB PM3 Device Programmer 30.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 30.12 Third-Party Development Tools 31.0 40 MHz Electrical Characteristics 31.1 DC Characteristics Table 31-1: Operating MIPS vs. Voltage Table 31-2: Thermal Operating Conditions Table 31-3: Thermal Packaging Characteristics Table 31-4: DC Temperature and Voltage Specifications Table 31-5: DC Characteristics: Operating Current (Idd) Table 31-6: DC Characteristics: Idle Current (Iidle) Table 31-7: DC Characteristics: Power-Down Current (Ipd) Table 31-8: DC Characteristics: I/O Pin Input Specifications TABLE 31-9: DC Characteristics: I/O Pin Output Specifications Table 31-10: Electrical Characteristics: BOR Table 31-11: Electrical Characteristics: HVD Table 31-12: DC Characteristics: Program Memory Table 31-13: Comparator Specifications Table 31-14: Comparator Voltage Reference Specifications Table 31-15: Internal Voltage Regulator Specifications 31.2 AC Characteristics and Timing Parameters Figure 31-1: Load Conditions for Device Timing Specifications Table 31-16: Capacitive Loading Requirements on Output Pins Figure 31-2: External Clock Timing Table 31-17: External Clock Timing Requirements Table 31-18: PLL Clock Timing Specifications Table 31-19: Internal FRC Accuracy Table 31-20: Internal LPRC Accuracy Figure 31-3: I/O Timing Characteristics Table 31-21: I/O Timing Requirements Figure 31-4: Power-On Reset Timing Characteristics Figure 31-5: External Reset Timing Characteristics Table 31-22: Resets Timing Figure 31-6: Timer1, 2, 3, 4, 5 External Clock Timing Characteristics Table 31-23: Timer1 External Clock Timing Requirements Table 31-24: Timer2, 3, 4, 5 External Clock Timing Requirements Figure 31-7: Input Capture (CAPx) Timing Characteristics Table 31-25: Input Capture Module Timing Requirements Figure 31-8: Output Compare Module (OCx) Timing Characteristics Table 31-26: Output Compare Module Timing Requirements Figure 31-9: OCx/PWM Module Timing Characteristics Table 31-27: Simple OCx/PWM Mode Timing Requirements Figure 31-10: SPIx Module Master Mode (CKE = 0) Timing Characteristics Table 31-28: SPIx Master Mode (CKE = 0) Timing Requirements Figure 31-11: SPIx Module Master Mode (CKE = 1) Timing Characteristics Table 31-29: SPIx Module Master Mode (CKE = 1) Timing Requirements Figure 31-12: SPIx Module Slave Mode (CKE = 0) Timing Characteristics Table 31-30: SPIx Module Slave Mode (CKE = 0) Timing Requirements Figure 31-13: SPIx Module Slave Mode (CKE = 1) Timing Characteristics Table 31-31: SPIx Module Slave Mode (CKE = 1) Timing Requirements Figure 31-14: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode) Figure 31-15: I2Cx Bus Data Timing Characteristics (Master Mode) Table 31-32: I2Cx Bus Data Timing Requirements (Master Mode) Figure 31-16: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode) Figure 31-17: I2Cx Bus Data Timing Characteristics (Slave Mode) Table 31-33: I2Cx Bus Data Timing Requirements (Slave Mode) Table 31-34: ADC Module Specifications Table 31-35: 10-bit Conversion Rate Parameters Table 31-36: Analog-to-Digital Conversion Timing Requirements Figure 31-18: Analog-to-Digital Conversion (10-bit Mode) Timing Characteristics (ASAM = 0, SSRC<2:0> = 000) Figure 31-19: Analog-to-Digital Conversion (10-bit mode) Timing Characteristics (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) Figure 31-20: Parallel Slave Port Timing Table 31-37: Parallel Slave Port Requirements Figure 31-21: Parallel Master Port Read Timing Diagram Table 31-38: Parallel Master Port Read Timing Requirements Figure 31-22: Parallel Master Port Write Timing Diagram Table 31-39: Parallel Master Port Write Timing Requirements Table 31-40: OTG Electrical Specifications TABLE 31-41: CTMU Current Source Specifications Figure 31-23: EJTAG Timing Characteristics Table 31-42: EJTAG Timing Requirements 32.0 50 MHz Electrical Characteristics 32.1 DC Characteristics Table 32-1: Operating MIPS vs. Voltage Table 32-2: DC Characteristics: Operating Current (Idd) Table 32-3: DC Characteristics: Idle Current (Iidle) Table 32-4: DC Characteristics: Power-Down Current (Ipd) 32.2 AC Characteristics and Timing Parameters Table 32-5: External Clock Timing Requirements Table 32-6: SPIx Master Mode (CKE = 0) Timing Requirements Table 32-7: SPIx Module Master Mode (CKE = 1) Timing Requirements Table 32-8: SPIx Module Slave Mode (CKE = 0) Timing Requirements Table 32-9: SPIx Module Slave Mode (CKE = 1) Timing Requirements 33.0 DC and AC Device Characteristics Graphs FIGURE 33-1: Voh – 4x Driver Pins FIGURE 33-2: Voh – 8x Driver Pins FIGURE 33-3: Vol – 4x Driver Pins FIGURE 33-4: Vol – 8x Driver Pins FIGURE 33-5: Typical CTMU Temperature DIODE Forward Voltage 34.0 Packaging Information 34.1 Package Marking Information 34.2 Package Details INDEX Appendix A: Revision History TABLE A-1: Major Section Updates TABLE A-2: Major Section Updates TABLE A-3: Major Section Updates TABLE A-4: Major Section Updates The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System AMERICAS Corporate Office Atlanta Austin, TX Boston Chicago Dallas Detroit Houston, TX Indianapolis Los Angeles Raleigh, NC New York, NY San Jose, CA Canada - Toronto ASIA/PACIFIC Australia - Sydney China - Beijing China - Chengdu China - Chongqing China - Dongguan China - Guangzhou China - Hangzhou China - Hong Kong SAR China - Nanjing China - Qingdao China - Shanghai China - Shenyang China - Shenzhen China - Suzhou China - Wuhan China - Xian China - Xiamen China - Zhuhai ASIA/PACIFIC India - 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