Datasheet AD817 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | High Speed, Low Power Wide Supply Range Amplifier |
| Pages / Page | 12 / 10 — AD817. OFFSET NULLING. AD817 SETTLING TIME. –10. OUTPUT SWING – Volts. … |
| Revision | B |
| File Format / Size | PDF / 226 Kb |
| Document Language | English |
AD817. OFFSET NULLING. AD817 SETTLING TIME. –10. OUTPUT SWING – Volts. 0.20. 0.15. 0.10. 0.05. OF FINAL VALUE. SETTLING TIME TO %. 100. 150. 200
Model Line for this Datasheet
Text Version of Document
AD817 OFFSET NULLING
Measuring the rapid settling time of AD817 (45 ns to 0.1% and The input offset voltage of the AD817 is inherently very low. 70 ns to 0.01%–10 V step) requires applying an input pulse with However, if additional nulling is required, the circuit shown in a very fast edge and an extremely flat top. With the AD817 con- Figure 32 can be used. The null range of the AD817 in this con- figured in a gain of –1, a clamped false summing junction re- figuration is ± 15 mV. sponds when the output error is within the sum of two diode voltages (ª1 volt). The signal is then amplified 20 times by a
AD817 SETTLING TIME
clamped amplifier whose output is connected directly to a sam- Settling time is comprised primarily of two regions. The first is pling oscilloscope. Figures 33 and 34 show the settling time of the slew time in which the amplifier is overdriven, where the the AD817, with a 10 volt step applied. output voltage rate of change is at its maximum. The second is the linear time period required for the amplifier to settle to
0
within a specified percent of the final value.
–2 –4 10 –6 8 –8 6 –10 OUTPUT SWING – Volts 4 2 0.20 0 0.15 OUTPUT SWING – Volts 0.10 0.05 0.05 0 0 OF FINAL VALUE 0.05 0.05 SETTLING TIME TO % 0.10 0 50 100 150 200 250 300 350 400 0.15 OF FINAL VALUE 0.20
Figure 34. Settling Time in ns 0 V to –10 V
SETTLING TIME TO % 0 50 100 150 200 250 300 350 400
Figure 33. Settling Time in ns 0 V to +10 V
2
×
HP2835 ERROR AMPLIFIER 1M
Ω
15pF V OUTPUT
×
10 ERROR 5 3 100
Ω
2
×
HP2835 AD829 SETTLING 6 OUTPUT 0.47
µ
F 4 2 SHORT, DIRECT 7 CONNECTION TO 0.01
µ
F TEKTRONIX TYPE 11402 0.01
µ
F OSCILLOSCOPE PREAMP ERROR INPUT SECTION 0.47
µ
F SIGNAL OUTPUT –V +V S S 100
Ω
1.9k
Ω
0 TO
±
10V NOTE: POWER USE CIRCUIT BOARD FALSE SUPPLY EI&S WITH GROUND PLANE NULL DL1A05GM SUMMING ADJUST MERCURY RELAY NODE 7, 8 1k
Ω
100
Ω
500
Ω
1k
Ω
2 50
Ω
13 DEVICE TTL LEVEL COAX 5–18pF UNDER SIGNAL TEKTRONIX P6201 1, 14 CABLE 500
Ω
TEST GENERATOR FET PROBE TO 50Hz 2 TEKTRONIX TYPE OUTPUT 50
Ω
AD817 11402 6 10pF OSCILLOSCOPE 3 7 SCOPE PROBE PREAMP INPUT 4 CAPACITANCE SECTION 2.2 DIGITAL
µ
F 0.01
µ
F GROUND 2.2
µ
F 0.01
µ
F +VS ANALOG GROUND –VS
Figure 35. Settling Time Test Circuit –10– REV. B
Measuring the rapid settling time of AD817 (45 ns to 0.1% and The input offset voltage of the AD817 is inherently very low. 70 ns to 0.01%–10 V step) requires applying an input pulse with However, if additional nulling is required, the circuit shown in a very fast edge and an extremely flat top. With the AD817 con- Figure 32 can be used. The null range of the AD817 in this con- figured in a gain of –1, a clamped false summing junction re- figuration is ± 15 mV. sponds when the output error is within the sum of two diode voltages (ª1 volt). The signal is then amplified 20 times by a
AD817 SETTLING TIME
clamped amplifier whose output is connected directly to a sam- Settling time is comprised primarily of two regions. The first is pling oscilloscope. Figures 33 and 34 show the settling time of the slew time in which the amplifier is overdriven, where the the AD817, with a 10 volt step applied. output voltage rate of change is at its maximum. The second is the linear time period required for the amplifier to settle to
0
within a specified percent of the final value.
–2 –4 10 –6 8 –8 6 –10 OUTPUT SWING – Volts 4 2 0.20 0 0.15 OUTPUT SWING – Volts 0.10 0.05 0.05 0 0 OF FINAL VALUE 0.05 0.05 SETTLING TIME TO % 0.10 0 50 100 150 200 250 300 350 400 0.15 OF FINAL VALUE 0.20
Figure 34. Settling Time in ns 0 V to –10 V
SETTLING TIME TO % 0 50 100 150 200 250 300 350 400
Figure 33. Settling Time in ns 0 V to +10 V
2
×
HP2835 ERROR AMPLIFIER 1M
Ω
15pF V OUTPUT
×
10 ERROR 5 3 100
Ω
2
×
HP2835 AD829 SETTLING 6 OUTPUT 0.47
µ
F 4 2 SHORT, DIRECT 7 CONNECTION TO 0.01
µ
F TEKTRONIX TYPE 11402 0.01
µ
F OSCILLOSCOPE PREAMP ERROR INPUT SECTION 0.47
µ
F SIGNAL OUTPUT –V +V S S 100
Ω
1.9k
Ω
0 TO
±
10V NOTE: POWER USE CIRCUIT BOARD FALSE SUPPLY EI&S WITH GROUND PLANE NULL DL1A05GM SUMMING ADJUST MERCURY RELAY NODE 7, 8 1k
Ω
100
Ω
500
Ω
1k
Ω
2 50
Ω
13 DEVICE TTL LEVEL COAX 5–18pF UNDER SIGNAL TEKTRONIX P6201 1, 14 CABLE 500
Ω
TEST GENERATOR FET PROBE TO 50Hz 2 TEKTRONIX TYPE OUTPUT 50
Ω
AD817 11402 6 10pF OSCILLOSCOPE 3 7 SCOPE PROBE PREAMP INPUT 4 CAPACITANCE SECTION 2.2 DIGITAL
µ
F 0.01
µ
F GROUND 2.2
µ
F 0.01
µ
F +VS ANALOG GROUND –VS
Figure 35. Settling Time Test Circuit –10– REV. B
