Datasheet HMC903LP3E (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | GaAs, pHEMT, MMIC, Low Noise Amplifier, 6 GHz to 17 GHz |
| Pages / Page | 13 / 10 — HMC903LP3E. Data Sheet. APPLICATIONS INFORMATION. RECOMMENDED BIAS … |
| Revision | I |
| File Format / Size | PDF / 312 Kb |
| Document Language | English |
HMC903LP3E. Data Sheet. APPLICATIONS INFORMATION. RECOMMENDED BIAS SEQUENCE DURING POWER. DOWN. RECOMMENDED BIAS SEQUENCE DURING
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HMC903LP3E Data Sheet APPLICATIONS INFORMATION
Figure 22 shows the basic connections for operating the
RECOMMENDED BIAS SEQUENCE DURING POWER
HMC903LP3E. Both the RFIN and RFOUT ports have on-chip
DOWN
dc block capacitors that eliminate the need for external ac The recommended bias sequence to power down the coupling capacitors. HMC903LP3E is as follows: The HMC903LP3E has VGG1 and VGG2 optional gate bias pins. 1. Turn off the RF signal. When these pins are left open, the amplifier runs in self biased 2. Decrease V operation with a typical I GG1 and VGG2 to −2 V to achieve a typical IDQ = DQ = 80 mA, when VDD1/VDD2 = 3.5 V. 0 mA. When using the VGG1 and VGG2 gate bias pins, fol ow the 3. Decrease V recommended bias sequencing so that the amplifier is not DD1 and VDD2 to 0 V. 4. Increase V damaged. GG1 and VGG2 to 0 V.
RECOMMENDED BIAS SEQUENCE DURING
Unless otherwise noted, all measurements and data shown were
POWER UP
taken using the typical application circuit (see Figure 23), with the evaluation board (see Figure 22) and biased per the conditions The recommended bias sequence to power up the in this section. The VDD1 and VDD2 pins are connected together; HMC903LP3E is as follows: similarly, the VGG1 and VGG2 pins are also connected together. The 1. Connect to GND. bias conditions shown in this section are the operating points 2. Set V recommended to optimize the overall performance. Operation GG1 and VGG2 to −2 V. 3. Set V using other bias conditions may provide performance that differs DD1 and VDD2 to 3.5 V. 4. Increase V from what is shown in this data sheet. GG1 and VGG2 to achieve a typical IDQ = 80 mA. 5. Apply the RF signal. Decreasing the VDD1 and VDD2 levels has negligible effect on the gain and noise figure performance; however, they reduce the P1dB. This behavior is shown in Figure 8 to Figure 20. For applications where the P1dB requirement is not stringent, the HMC903LP3E can be down biased to reduce power consumption. Rev. I | Page 10 of 13 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications 6 GHz to 16 GHz Frequency Range 16 GHz to 17 GHz Frequency Range Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Recommended Bias Sequence During Power Up Recommended Bias Sequence During Power Down Evaluation PCB Typical Application Circuits Outline Dimensions Ordering Guide
HMC903LP3E Data Sheet APPLICATIONS INFORMATION
Figure 22 shows the basic connections for operating the
RECOMMENDED BIAS SEQUENCE DURING POWER
HMC903LP3E. Both the RFIN and RFOUT ports have on-chip
DOWN
dc block capacitors that eliminate the need for external ac The recommended bias sequence to power down the coupling capacitors. HMC903LP3E is as follows: The HMC903LP3E has VGG1 and VGG2 optional gate bias pins. 1. Turn off the RF signal. When these pins are left open, the amplifier runs in self biased 2. Decrease V operation with a typical I GG1 and VGG2 to −2 V to achieve a typical IDQ = DQ = 80 mA, when VDD1/VDD2 = 3.5 V. 0 mA. When using the VGG1 and VGG2 gate bias pins, fol ow the 3. Decrease V recommended bias sequencing so that the amplifier is not DD1 and VDD2 to 0 V. 4. Increase V damaged. GG1 and VGG2 to 0 V.
RECOMMENDED BIAS SEQUENCE DURING
Unless otherwise noted, all measurements and data shown were
POWER UP
taken using the typical application circuit (see Figure 23), with the evaluation board (see Figure 22) and biased per the conditions The recommended bias sequence to power up the in this section. The VDD1 and VDD2 pins are connected together; HMC903LP3E is as follows: similarly, the VGG1 and VGG2 pins are also connected together. The 1. Connect to GND. bias conditions shown in this section are the operating points 2. Set V recommended to optimize the overall performance. Operation GG1 and VGG2 to −2 V. 3. Set V using other bias conditions may provide performance that differs DD1 and VDD2 to 3.5 V. 4. Increase V from what is shown in this data sheet. GG1 and VGG2 to achieve a typical IDQ = 80 mA. 5. Apply the RF signal. Decreasing the VDD1 and VDD2 levels has negligible effect on the gain and noise figure performance; however, they reduce the P1dB. This behavior is shown in Figure 8 to Figure 20. For applications where the P1dB requirement is not stringent, the HMC903LP3E can be down biased to reduce power consumption. Rev. I | Page 10 of 13 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications 6 GHz to 16 GHz Frequency Range 16 GHz to 17 GHz Frequency Range Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Recommended Bias Sequence During Power Up Recommended Bias Sequence During Power Down Evaluation PCB Typical Application Circuits Outline Dimensions Ordering Guide
