Datasheet HMC1121 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 4 W, GaAs, pHEMT, MMIC Power Amplifier, 5.5 GHz to 8.5 GHz |
| Pages / Page | 15 / 5 — Data Sheet. HMC1121. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GG1. … |
| Revision | A |
| File Format / Size | PDF / 393 Kb |
| Document Language | English |
Data Sheet. HMC1121. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. GG1. GG2. NIC 1. 30 NIC. NIC 2. 29 NIC. NIC 3. 28 NIC. NIC 4. 27 NIC. RFIN 5
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Data Sheet HMC1121 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 C C C C C GG1 DD GG2 DD C NI NI NI V V NI V NI V NI 40 39 38 37 36 35 34 33 32 31 NIC 1 30 NIC NIC 2 29 NIC NIC 3 28 NIC NIC 4 27 NIC RFIN 5 HMC1121 26 RFOUT NIC 6 TOP VIEW 25 NIC (Not to Scale) NIC 7 24 VDET NIC 8 23 VREF NIC 9 22 NIC NIC 10 21 NIC 11 12 13 14 15 16 17 18 19 20 C C 3 3 C C 4 C 4 C NI NI NI GG DD NI GG NI DD NI V V V V NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD. EXPOSED PAD MUST BE
-002
CONNECTED TO THE RF/DC GROUND.
529 13 Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 to 4, 6 to 13, 16, 18, 20 NC No Internal Connection. These pins and exposed ground pad must be connected to RF/dc to 22, 25, 27 to 31, 33, 35, ground. 38 to 40 5 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 3 for the RFIN interface schematic. 14, 17, 34, 37 VGG3, VGG4, Gate Controls for the Amplifier. Adjust VGG1 through VGG4 to achieve the recommended bias VGG2, VGG1 current. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required. See Figure 5 for the VGG1 to VGG4 interface schematic. 15, 19, 32, 36 VDD3, VDD4, Drain Biases for the Amplifier. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required. VDD2, VDD1 See Figure 8 for the VDD1 to VDD4 interface schematic. 23 VREF Voltage Reference. This pin is the dc bias of the diode biased through the external resistor and is used for the temperature compensation of VDET. See Figure 7 for the VREF interface schematic. 24 VDET Voltage Detection. This pin is the dc voltage representing the RF output power rectified by the diode that is biased through an external resistor. See Figure 4 for the VDET interface schematic. 26 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground. Rev. A | Page 5 of 15 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Recommended Bias Sequence During Power-Up During Power-Down Typical Application Circuit Evaluation Board Bill of Materials Evaluation Board Schematic Outline Dimensions Ordering Guide
Data Sheet HMC1121 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 C C C C C GG1 DD GG2 DD C NI NI NI V V NI V NI V NI 40 39 38 37 36 35 34 33 32 31 NIC 1 30 NIC NIC 2 29 NIC NIC 3 28 NIC NIC 4 27 NIC RFIN 5 HMC1121 26 RFOUT NIC 6 TOP VIEW 25 NIC (Not to Scale) NIC 7 24 VDET NIC 8 23 VREF NIC 9 22 NIC NIC 10 21 NIC 11 12 13 14 15 16 17 18 19 20 C C 3 3 C C 4 C 4 C NI NI NI GG DD NI GG NI DD NI V V V V NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD. EXPOSED PAD MUST BE
-002
CONNECTED TO THE RF/DC GROUND.
529 13 Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 to 4, 6 to 13, 16, 18, 20 NC No Internal Connection. These pins and exposed ground pad must be connected to RF/dc to 22, 25, 27 to 31, 33, 35, ground. 38 to 40 5 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω. See Figure 3 for the RFIN interface schematic. 14, 17, 34, 37 VGG3, VGG4, Gate Controls for the Amplifier. Adjust VGG1 through VGG4 to achieve the recommended bias VGG2, VGG1 current. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required. See Figure 5 for the VGG1 to VGG4 interface schematic. 15, 19, 32, 36 VDD3, VDD4, Drain Biases for the Amplifier. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required. VDD2, VDD1 See Figure 8 for the VDD1 to VDD4 interface schematic. 23 VREF Voltage Reference. This pin is the dc bias of the diode biased through the external resistor and is used for the temperature compensation of VDET. See Figure 7 for the VREF interface schematic. 24 VDET Voltage Detection. This pin is the dc voltage representing the RF output power rectified by the diode that is biased through an external resistor. See Figure 4 for the VDET interface schematic. 26 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω. See Figure 6 for the RFOUT interface schematic. EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground. Rev. A | Page 5 of 15 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Recommended Bias Sequence During Power-Up During Power-Down Typical Application Circuit Evaluation Board Bill of Materials Evaluation Board Schematic Outline Dimensions Ordering Guide
