Datasheet HMC637ALP5E (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | GaAs, pHEMT, MMIC, 1 W Power Amplifier, 0.1 GHz to 6 GHz |
| Pages / Page | 11 / 3 — Data Sheet. HMC637ALP5E. SPECIFICATIONS ELECTRICAL SPECIFICATIONS. Table … |
| Revision | C |
| File Format / Size | PDF / 269 Kb |
| Document Language | English |
Data Sheet. HMC637ALP5E. SPECIFICATIONS ELECTRICAL SPECIFICATIONS. Table 1. Parameter Symbol. Test. Conditions/Comments. Min. Typ. Max
Model Line for this Datasheet
Text Version of Document
Data Sheet HMC637ALP5E SPECIFICATIONS ELECTRICAL SPECIFICATIONS
TA = 25°C, drain bias voltage (VDD) = 12 V, gate bias voltage (VGG2) = 5 V, supply current (IDD) = 400 mA (adjust VGG1 between −2 V to 0 V to achieve IDD = 400 mA typical), 50 Ω system, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Units
FREQUENCY RANGE 0.1 6 GHz GAIN 12 13 dB Gain Flatness ±0.75 dB Gain Variation Over Temperature 0.015 dB/°C RETURN LOSS Input 12 dB Output 15 dB OUTPUT Output Power for 1 dB Compression P1dB 27 29 dBm Saturated Output Power PSAT 31 dBm Output Third-Order Intercept OIP3 POUT per tone = 10 dBm, 1 MHz spacing 44 dBm NOISE FIGURE 12 dB 2.0 GHz to 6.0 GHz 5 dB SUPPLY CURRENT IDD 320 400 480 mA Drain Bias Voltage1 VDD IDD = 400 mA 11.5 V 12.0 V 12.5 V 1 VGG1 set initially for nominal bias condition of VDD = 12 V and VGG2 = 5 V to achieve IDD = 400 mA typical; then adjusting VDD ±0.5 V from 12 V to measure IDD variation. Rev. C | Page 3 of 11 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Applications Information Evaluation PCB List of Materials for PCB EV1HMC637ALP5E Outline Dimensions Ordering Guide
TA = 25°C, drain bias voltage (VDD) = 12 V, gate bias voltage (VGG2) = 5 V, supply current (IDD) = 400 mA (adjust VGG1 between −2 V to 0 V to achieve IDD = 400 mA typical), 50 Ω system, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Units
FREQUENCY RANGE 0.1 6 GHz GAIN 12 13 dB Gain Flatness ±0.75 dB Gain Variation Over Temperature 0.015 dB/°C RETURN LOSS Input 12 dB Output 15 dB OUTPUT Output Power for 1 dB Compression P1dB 27 29 dBm Saturated Output Power PSAT 31 dBm Output Third-Order Intercept OIP3 POUT per tone = 10 dBm, 1 MHz spacing 44 dBm NOISE FIGURE 12 dB 2.0 GHz to 6.0 GHz 5 dB SUPPLY CURRENT IDD 320 400 480 mA Drain Bias Voltage1 VDD IDD = 400 mA 11.5 V 12.0 V 12.5 V 1 VGG1 set initially for nominal bias condition of VDD = 12 V and VGG2 = 5 V to achieve IDD = 400 mA typical; then adjusting VDD ±0.5 V from 12 V to measure IDD variation. Rev. C | Page 3 of 11 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Applications Information Evaluation PCB List of Materials for PCB EV1HMC637ALP5E Outline Dimensions Ordering Guide
