Datasheet AD8313 (Analog Devices) - 10

AD8313 Data Sheet 100.00 CH. 1 AND CH. 2: 200mV/DIV AVERAGE: 50 SAMPLES V 13.7mA S = +5.5V CH. 1 10.00 VS = +2.7V CH. 2 PULSED RF 1.00 CH. 1 GND 100MHz, –45dBm VPOS = +3V VPOS = +5V CH. 2 GND SUPPLY CURRENT (mA) 0.10 40
µ
A 20
µ
A HORIZONTAL: 50ns/DIV
01085-C-019
0.01 0 1 2 3 4 5 PWDN VOLTAGE (V)
01085-C-016 Figure 16. Typical Supply Current vs. PWDN Voltage Figure 18. Response Time, No Signal to –45 dBm
CH. 1 AND CH. 2: 1V/DIV CH. 3: 5V/DIV CH. 1 & CH. 2: 500mV/DIV AVERAGE: 50 SAMPLES V V OUT @ S = +5.5V VS = +5.5V CH. 1 CH. 1 GND VS = +2.7V CH. 2 V CH. 1 GND OUT @ VS = +2.7V CH. 2 GND PULSED RF CH. 2 GND 100MHz, 0dBm PWDN CH. 3 GND HORIZONTAL: 1
µ
s/DIV HORIZONTAL: 50ns/DIV
01085-C-017 01085-C-020 Figure 17. PWDN Response Time Figure 19. Response Time, No Signal to 0 dBm
HP8648B HP8112A 10MHz REF OUTPUT EXT TRIG OUT HP8648B SIGNAL PULSE SIGNAL 10MHz REF OUTPUT EXT TRIG TRIG HP8112A GENERATOR GENERATOR OUT GENERATOR PIN = 0dBm PULSE MODE IN OUT PULSE RF OUT PULSE GENERATOR MODULATION 10
Ω
TEK MODE TEK P6205 +V 1 VPOS VOUT 8 TDS784C S 0.1
µ
F FET PROBE SCOPE TRIG RF OUT 0.01
µ
F AD8313 2 INHI VSET 7 RF –6dB 54.9
Ω
SPLITTER 0.01
µ
F 0603 SIZE SURFACE 3 INLO COMM –6dB TEK 6 MOUNT COMPONENTS ON 10
Ω
TEK P6205 A LOW LEAKAGE PC BOARD +V 1 VPOS VOUT 8 TDS784C S FET PROBE 10
Ω
0.1
µ
F SCOPE AD8313 TRIG +V 0.01
µ
F S 4 VPOS PWDN 5 0.1
µ
F 2 INHI VSET 7
01085-C-018
54.9
Ω
0.01
µ
F 0603 SIZE SURFACE
Figure 20. Test Setup for PWDN Response Time
3 INLO COMM 6 MOUNT COMPONENTS ON A LOW LEAKAGE PC BOARD 10
Ω
+VS 4 VPOS PWDN 5 0.1
µ
F
01085-C-021 Figure 21. Test Setup for RSSI Mode Pulse Response Rev. E | Page 10 of 24 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Description Typical Performance Characteristics Circuit Description Interfaces Power-Down Interface, PWDN Signal Inputs, INHI, INLO Logarithmic/Error Output, VOUT Setpoint Interface, VSET Applications Information Basic Connections for Log (RSSI) Mode Operating in Controller Mode Input Coupling Narrow-Band LC Matching Example at 100 MHz Adjusting the Log Slope Increasing Output Current Effect of Waveform Type on Intercept Evaluation Board Schematic and Layout General Operation Using the AD8009 Operational Amplifier Varying the Logarithmic Slope Operating in Controller Mode RF Burst Response Outline Dimensions Ordering Guide