Datasheet ADA4320-1 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Low Distortion, DOCSIS 3.0, Upstream CATV Line Driver |
| Pages / Page | 16 / 5 — TIMING REQUIREMENTS. Table 3. Parameter. Min. Typ. Max. Unit. tDS. VALID … |
| Revision | A |
| File Format / Size | PDF / 365 Kb |
| Document Language | English |
TIMING REQUIREMENTS. Table 3. Parameter. Min. Typ. Max. Unit. tDS. VALID DATA-WORD G1. MSB...LSB. VALID DATA-WORD G2. SDATA. tWH. CLK. tES. tEH
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Text Version of Document
ADA4320-1
TIMING REQUIREMENTS
Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.
Table 3. Parameter Min Typ Max Unit
Clock Pulse Width (tWH) 16 ns Clock Period (tC) 32 ns Setup Time SDATA vs. Clock (tDS) 5 ns Setup Time DATEN vs. Clock (tES) 16 ns Hold Time SDATA vs. Clock (tDH) 5 ns Hold Time DATEN vs. Clock (tEH) 3 ns Input 10% to 90% Rise and Fall Times, SDATA, DATEN, Clock 10 ns
tDS VALID DATA-WORD G1 MSB...LSB VALID DATA-WORD G2 SDATA tC tWH CLK tES tEH DATEN 8 CLOCK CYCLES GAIN TRANSFER (G1) GAIN TRANSFER (G2) TXEN ANALOG OUTPUT
02 0 7-
SIGNAL AMPLITUDE (p-p)
70 08 Figure 2. Serial Interface Timing
VALID DATA BIT SDATA MSB MSB – 1 MSB – 2 tDS tDH
3
CLK
00 7- 70 08 Figure 3. SDATA Timing Rev. A | Page 5 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE
TIMING REQUIREMENTS
Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.
Table 3. Parameter Min Typ Max Unit
Clock Pulse Width (tWH) 16 ns Clock Period (tC) 32 ns Setup Time SDATA vs. Clock (tDS) 5 ns Setup Time DATEN vs. Clock (tES) 16 ns Hold Time SDATA vs. Clock (tDH) 5 ns Hold Time DATEN vs. Clock (tEH) 3 ns Input 10% to 90% Rise and Fall Times, SDATA, DATEN, Clock 10 ns
tDS VALID DATA-WORD G1 MSB...LSB VALID DATA-WORD G2 SDATA tC tWH CLK tES tEH DATEN 8 CLOCK CYCLES GAIN TRANSFER (G1) GAIN TRANSFER (G2) TXEN ANALOG OUTPUT
02 0 7-
SIGNAL AMPLITUDE (p-p)
70 08 Figure 2. Serial Interface Timing
VALID DATA BIT SDATA MSB MSB – 1 MSB – 2 tDS tDH
3
CLK
00 7- 70 08 Figure 3. SDATA Timing Rev. A | Page 5 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE
