Datasheet AD8275 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | G = 0.2, Level Translation, 16-Bit ADC Driver |
| Pages / Page | 16 / 9 — Data Sheet. AD8275. ) s. +SR. (% T. 3.3V. E (V/. –SR. VER. –40. –20. 100. … |
| Revision | B |
| File Format / Size | PDF / 541 Kb |
| Document Language | English |
Data Sheet. AD8275. ) s. +SR. (% T. 3.3V. E (V/. –SR. VER. –40. –20. 100. 120. 140. 160. TEMPERATURE (°C). CAPACITANCE (pF). CLOAD = 47pF. 2kΩ. NO LOAD. 600Ω
Model Line for this Datasheet
Text Version of Document
Data Sheet AD8275 40 60 35 50 30 ) s +SR ) 40 µ 25 (% T 3.3V E (V/ O T –SR A 20 O 30 R SH 5V EW 15 VER SL O 20 10 10 5
021 024 07546-
0
07546-
0 –40 –20 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 TEMPERATURE (°C) CAPACITANCE (pF)
Figure 23. Slew Rate vs. Temperature Figure 26. Small Signal Overshoot vs. Capacitive Load, No Resistive Load
60 CLOAD = 47pF 2kΩ NO LOAD 50 ) 40 (% V T 600Ω O /DI 3.3V O 30 SH 20mV 5V VER O 20 10kΩ 10
022 025 07546- 07546-
0 1µs/DIV 0 20 40 60 80 100 120 140 160 CAPACITANCE (pF)
Figure 24. Small Signal Step Response for Various Resistive Loads Figure 27. Small Signal Overshoot vs. Capacitive Load, (Step Responses Staggered for Clarity) 600 Ω in Parallel with Capacitive Load
60 NO RESISTIVE LOAD 20pF 100pF 50 ) 40 NO CAP (% V T O 3.3V /DI O 30 SH 20mV 5V VER O 20 47pF 10
023 026 07546- 07546-
0 1µs/DIV 0 20 40 60 80 100 120 140 160 CAPACITANCE (pF)
Figure 25. Small Signal Pulse Response for Various Capacitive Loads Figure 28. Small Signal Overshoot vs. Capacitive Load, (Step Responses Staggered for Clarity) 2 kΩ in Parallel with Capacitive Load Rev. B | Page 9 of 16 Document Outline Features Applications Pin Configuration Typical Application General Description Revision History Specifications Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Connection Power Supplies Reference Common-Mode Input Voltage Range Input Protection Configurations Applications Information Driving a Single-Ended ADC Differential Outputs Increasing Input Impedance AC Coupling Using the AD8275 as a Level Translator in a Data Acquisition System Outline Dimensions Ordering Guide
021 024 07546-
0
07546-
0 –40 –20 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 TEMPERATURE (°C) CAPACITANCE (pF)
Figure 23. Slew Rate vs. Temperature Figure 26. Small Signal Overshoot vs. Capacitive Load, No Resistive Load
60 CLOAD = 47pF 2kΩ NO LOAD 50 ) 40 (% V T 600Ω O /DI 3.3V O 30 SH 20mV 5V VER O 20 10kΩ 10
022 025 07546- 07546-
0 1µs/DIV 0 20 40 60 80 100 120 140 160 CAPACITANCE (pF)
Figure 24. Small Signal Step Response for Various Resistive Loads Figure 27. Small Signal Overshoot vs. Capacitive Load, (Step Responses Staggered for Clarity) 600 Ω in Parallel with Capacitive Load
60 NO RESISTIVE LOAD 20pF 100pF 50 ) 40 NO CAP (% V T O 3.3V /DI O 30 SH 20mV 5V VER O 20 47pF 10
023 026 07546- 07546-
0 1µs/DIV 0 20 40 60 80 100 120 140 160 CAPACITANCE (pF)
Figure 25. Small Signal Pulse Response for Various Capacitive Loads Figure 28. Small Signal Overshoot vs. Capacitive Load, (Step Responses Staggered for Clarity) 2 kΩ in Parallel with Capacitive Load Rev. B | Page 9 of 16 Document Outline Features Applications Pin Configuration Typical Application General Description Revision History Specifications Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Connection Power Supplies Reference Common-Mode Input Voltage Range Input Protection Configurations Applications Information Driving a Single-Ended ADC Differential Outputs Increasing Input Impedance AC Coupling Using the AD8275 as a Level Translator in a Data Acquisition System Outline Dimensions Ordering Guide
