Datasheet AD629 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | High Common-Mode Voltage, Difference Amplifier |
| Pages / Page | 16 / 4 — AD629. ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating. DIE SIZE: … |
| Revision | C |
| File Format / Size | PDF / 413 Kb |
| Document Language | English |
AD629. ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating. DIE SIZE: 1655µm (X) by 2465µm (Y). Table 3. Pin Pad Coordinates
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AD629 ABSOLUTE MAXIMUM RATINGS Table 2. 1a 1b Parameter Rating 2
Supply Voltage, VS ±18 V Internal Power Dissipation1
7
8-Lead PDIP (N) See Figure 4 8-Lead SOIC (R) See Figure 4 Input Voltage Range, Continuous ±300 V
Y
Common-Mode and Differential, 10 sec ±500 V Output Short-Circuit Duration Indefinite Pin 1 and Pin 5 –VS − 0.3 V to +VS + 0.3 V
3
Maximum Junction Temperature 150°C Operating Temperature Range −55°C to +125°C
4 6b
Storage Temperature Range −65°C to +150°C
6a
Lead Temperature (Soldering 60 sec) 300°C
5a 5b
1 Specification is for device in free air:
X
41 0 3- 8-Lead PDIP, θJA = 100°C/W;
DIE SIZE: 1655µm (X) by 2465µm (Y)
078 0 8-Lead SOIC, θJA = 155°C/W. Figure 5. Metallization Photograph Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
Table 3. Pin Pad Coordinates
rating only; functional operation of the device at these or any
Coordinates1
other conditions above those indicated in the operational
Pad Pin X Y Description
section of this specification is not implied. Exposure to absolute 1a REF(−) −677 +1082 For the die model, either maximum rating conditions for extended periods may affect 1b −534 +1084 pad can be bonded because device reliability. 1a and 1b are internally shorted.
2.0 T
2 −IN −661 +939
J = 150°C )
3 +IN −661 −658
W 8-LEAD PDIP (
4 −V
1.5
S +680 −800
TION
5a REF(+) +396 −1084 For the die model, either
A P
5b +538 −1084 pad can be bonded because
ISSI
5a and 5b are internally
D R 1.0 E
shorted.
W
6a OUTPUT +681 −950 For the die model, both
M PO 8-LEAD SOIC
6b +681 −807 pads must be bonded
MU 0.5
because 6a and 6b are not
XI
internally shorted.
MA
04 0 7 +VS +680 +612 3- 78
0
00
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
1 All coordinates are with respect to the center of the die.
AMBIENT TEMPERATURE (°C) ESD CAUTION
Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP Rev. C | Page 4 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS BASIC CONNECTIONS SINGLE-SUPPLY OPERATION SYSTEM-LEVEL DECOUPLING AND GROUNDING USING A LARGE SENSE RESISTOR OUTPUT FILTERING OUTPUT CURRENT AND BUFFERING A GAIN OF 19 DIFFERENTIAL AMPLIFIER ERROR BUDGET ANALYSIS EXAMPLE 1 ERROR BUDGET ANALYSIS EXAMPLE 2 OUTLINE DIMENSIONS ORDERING GUIDE
AD629 ABSOLUTE MAXIMUM RATINGS Table 2. 1a 1b Parameter Rating 2
Supply Voltage, VS ±18 V Internal Power Dissipation1
7
8-Lead PDIP (N) See Figure 4 8-Lead SOIC (R) See Figure 4 Input Voltage Range, Continuous ±300 V
Y
Common-Mode and Differential, 10 sec ±500 V Output Short-Circuit Duration Indefinite Pin 1 and Pin 5 –VS − 0.3 V to +VS + 0.3 V
3
Maximum Junction Temperature 150°C Operating Temperature Range −55°C to +125°C
4 6b
Storage Temperature Range −65°C to +150°C
6a
Lead Temperature (Soldering 60 sec) 300°C
5a 5b
1 Specification is for device in free air:
X
41 0 3- 8-Lead PDIP, θJA = 100°C/W;
DIE SIZE: 1655µm (X) by 2465µm (Y)
078 0 8-Lead SOIC, θJA = 155°C/W. Figure 5. Metallization Photograph Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
Table 3. Pin Pad Coordinates
rating only; functional operation of the device at these or any
Coordinates1
other conditions above those indicated in the operational
Pad Pin X Y Description
section of this specification is not implied. Exposure to absolute 1a REF(−) −677 +1082 For the die model, either maximum rating conditions for extended periods may affect 1b −534 +1084 pad can be bonded because device reliability. 1a and 1b are internally shorted.
2.0 T
2 −IN −661 +939
J = 150°C )
3 +IN −661 −658
W 8-LEAD PDIP (
4 −V
1.5
S +680 −800
TION
5a REF(+) +396 −1084 For the die model, either
A P
5b +538 −1084 pad can be bonded because
ISSI
5a and 5b are internally
D R 1.0 E
shorted.
W
6a OUTPUT +681 −950 For the die model, both
M PO 8-LEAD SOIC
6b +681 −807 pads must be bonded
MU 0.5
because 6a and 6b are not
XI
internally shorted.
MA
04 0 7 +VS +680 +612 3- 78
0
00
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
1 All coordinates are with respect to the center of the die.
AMBIENT TEMPERATURE (°C) ESD CAUTION
Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP Rev. C | Page 4 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS BASIC CONNECTIONS SINGLE-SUPPLY OPERATION SYSTEM-LEVEL DECOUPLING AND GROUNDING USING A LARGE SENSE RESISTOR OUTPUT FILTERING OUTPUT CURRENT AND BUFFERING A GAIN OF 19 DIFFERENTIAL AMPLIFIER ERROR BUDGET ANALYSIS EXAMPLE 1 ERROR BUDGET ANALYSIS EXAMPLE 2 OUTLINE DIMENSIONS ORDERING GUIDE
