Datasheet LT8653S (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual Channel 2A, 42V, Synchronous Step-Down Silent Switcher 2 with 6.2μA Quiescent Current |
| Pages / Page | 32 / 10 — PIN FUNCTIONS D0 (Pin 1):. SW1 (Pin 7):. D1 (Pin 2):. SW2 (Pin 8):. PG2 … |
| Revision | A |
| File Format / Size | PDF / 2.2 Mb |
| Document Language | English |
PIN FUNCTIONS D0 (Pin 1):. SW1 (Pin 7):. D1 (Pin 2):. SW2 (Pin 8):. PG2 (Pin 3):. VCC (Pin 9):. PG1 (Pin 4):. BIAS (Pin 10):
Model Line for this Datasheet
Text Version of Document
link to page 16 link to page 16 LT8653S
PIN FUNCTIONS D0 (Pin 1):
Output Voltage Select Bit. D0 should be tied
SW1 (Pin 7):
The SW1 pin is the output of the Channel 1 high to VCC, low to GND or left open to select the desired internal power switches. Connect this pin to the induc- FB regulation voltage (see Table 1). tor. This node should be kept small on the PCB for good
D1 (Pin 2):
Output Voltage Select Bit. D1 should be tied performance. high to VCC, low to GND or left open to select the desired
SW2 (Pin 8):
The SW2 pin is the output of the Channel 2 FB regulation voltage (see Table 1). internal power switches. Connect this pin to the induc-
PG2 (Pin 3):
The PG2 pin is the open-drain output of an tor. This node should be kept small on the PCB for good internal comparator. PG2 remains low until the FB2 pin is performance. within ±7.5% of the final regulation voltage and there are
VCC (Pin 9):
Internal Regulator Bypass Pin. The inter- no fault conditions. PG2 is pulled low during VIN UVLO, nal power drivers and control circuits are powered from VCC UVLO, thermal shutdown or when the EN/UV pin is this voltage. VCC current will be supplied from BIAS if low. VBIAS > 3.1V, otherwise current will be drawn from VIN.
PG1 (Pin 4):
The PG1 pin is the open-drain output of an Voltage on VCC will vary between 2.8V and 3.3V when internal comparator. PG1 remains low until the FB1 pin is VBIAS is between 3.0V and 3.5V. Do not load the VCC pin within ±7.5% of the final regulation voltage and there are with external circuitry. no fault conditions. PG1 is pulled low during VIN UVLO,
BIAS (Pin 10):
The internal regulator will draw current VCC UVLO, thermal shutdown or when the EN/UV pin is from BIAS instead of VIN when BIAS is tied to a voltage low. higher than 3.1V. For output voltages of 3.3V and above
SYNC (Pin 5):
External Clock Synchronization Input. this pin should be tied to VOUT. If this pin is tied to a Ground this pin for low ripple Burst Mode operation at supply other than VOUT, use a 1µF local bypass capacitor low output loads. Apply a DC voltage of 2.8V or higher on this pin. or tie to VCC for forced continuous mode with spread
VC1 (Pin 11):
Channel 1 Error Amplifier Output and spectrum modulation. Float the SYNC pin for forced Switching Regulator Compensation Pin. Connect this pin continuous mode without spread spectrum modulation. to appropriate external components to compensate the When in forced continuous mode, the IQ wil increase regulator loop frequency response. Connect this pin to to several mA. Apply a clock source to the SYNC pin for VCC to use the default internal compensation. If internal synchronization to an external frequency. The LT8653S compensation is used, the burst mode quiescent current will be in forced continuous mode when an external fre- is only 2.5µA for Channel 1. If external compensation is quency is applied. used, the burst mode quiescent current is increased to
CLKOUT (Pin 6):
In forced continuous mode, the CLKOUT about 50µA for Channel 1. pin provides a 50% duty cycle square wave 90 degrees
FB1 (Pin 12):
The LT8653S regulates the FB1 pin to out of phase with Channel 1. This allows synchronization 800mV, 1.8V, 3.3V, or 5.0V depending on the state of with other regulators with up to four phases. When an the D0 and D1 pins. If set to 800mV, connect the feedback external clock is applied to the SYNC pin, the CLKOUT pin resistor divider tap to this pin. If set to 1.8V, 3.3V or 5.0V, will output a waveform with the same phase, duty cycle connect this pin directly to the output. and frequency as the SYNC waveform. In Burst Mode operation, the CLKOUT pin will be grounded. Float this pin if the CLKOUT function is not used. Rev. A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS D0 (Pin 1):
Output Voltage Select Bit. D0 should be tied
SW1 (Pin 7):
The SW1 pin is the output of the Channel 1 high to VCC, low to GND or left open to select the desired internal power switches. Connect this pin to the induc- FB regulation voltage (see Table 1). tor. This node should be kept small on the PCB for good
D1 (Pin 2):
Output Voltage Select Bit. D1 should be tied performance. high to VCC, low to GND or left open to select the desired
SW2 (Pin 8):
The SW2 pin is the output of the Channel 2 FB regulation voltage (see Table 1). internal power switches. Connect this pin to the induc-
PG2 (Pin 3):
The PG2 pin is the open-drain output of an tor. This node should be kept small on the PCB for good internal comparator. PG2 remains low until the FB2 pin is performance. within ±7.5% of the final regulation voltage and there are
VCC (Pin 9):
Internal Regulator Bypass Pin. The inter- no fault conditions. PG2 is pulled low during VIN UVLO, nal power drivers and control circuits are powered from VCC UVLO, thermal shutdown or when the EN/UV pin is this voltage. VCC current will be supplied from BIAS if low. VBIAS > 3.1V, otherwise current will be drawn from VIN.
PG1 (Pin 4):
The PG1 pin is the open-drain output of an Voltage on VCC will vary between 2.8V and 3.3V when internal comparator. PG1 remains low until the FB1 pin is VBIAS is between 3.0V and 3.5V. Do not load the VCC pin within ±7.5% of the final regulation voltage and there are with external circuitry. no fault conditions. PG1 is pulled low during VIN UVLO,
BIAS (Pin 10):
The internal regulator will draw current VCC UVLO, thermal shutdown or when the EN/UV pin is from BIAS instead of VIN when BIAS is tied to a voltage low. higher than 3.1V. For output voltages of 3.3V and above
SYNC (Pin 5):
External Clock Synchronization Input. this pin should be tied to VOUT. If this pin is tied to a Ground this pin for low ripple Burst Mode operation at supply other than VOUT, use a 1µF local bypass capacitor low output loads. Apply a DC voltage of 2.8V or higher on this pin. or tie to VCC for forced continuous mode with spread
VC1 (Pin 11):
Channel 1 Error Amplifier Output and spectrum modulation. Float the SYNC pin for forced Switching Regulator Compensation Pin. Connect this pin continuous mode without spread spectrum modulation. to appropriate external components to compensate the When in forced continuous mode, the IQ wil increase regulator loop frequency response. Connect this pin to to several mA. Apply a clock source to the SYNC pin for VCC to use the default internal compensation. If internal synchronization to an external frequency. The LT8653S compensation is used, the burst mode quiescent current will be in forced continuous mode when an external fre- is only 2.5µA for Channel 1. If external compensation is quency is applied. used, the burst mode quiescent current is increased to
CLKOUT (Pin 6):
In forced continuous mode, the CLKOUT about 50µA for Channel 1. pin provides a 50% duty cycle square wave 90 degrees
FB1 (Pin 12):
The LT8653S regulates the FB1 pin to out of phase with Channel 1. This allows synchronization 800mV, 1.8V, 3.3V, or 5.0V depending on the state of with other regulators with up to four phases. When an the D0 and D1 pins. If set to 800mV, connect the feedback external clock is applied to the SYNC pin, the CLKOUT pin resistor divider tap to this pin. If set to 1.8V, 3.3V or 5.0V, will output a waveform with the same phase, duty cycle connect this pin directly to the output. and frequency as the SYNC waveform. In Burst Mode operation, the CLKOUT pin will be grounded. Float this pin if the CLKOUT function is not used. Rev. A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
