Datasheet ADP5054 (Analog Devices) - 5

Data Sheet ADP5054 SPECIFICATIONS
VIN = 12 V, VVREG = 5.0 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 4.5 15.5 V PVIN1, PVIN2, PVIN3, PVIN4 pins QUIESCENT CURRENT PVIN1, PVIN2, PVIN3, PVIN4 pins Operating Quiescent Current IQ 4.7 5.3 mA No switching, all ENx pins high Shutdown Current ISHDN 20 35 μA All ENx pins low UNDERVOLTAGE LOCKOUT UVLO PVIN1, PVIN2, PVIN3, PVIN4 pins Threshold, Rising VUVLO_RISING 4.22 4.34 V Threshold, Falling VUVLO_FALLING 3.65 3.79 V Hysteresis VHYS 0.43 V OSCILLATOR CIRCUIT Switching Frequency fSW 570 600 630 kHz RT = 32.4 kΩ Switching Frequency Range 250 2000 kHz SYNC Input Input Clock Range fSYNC 250 2000 kHz Input Clock Pulse Width Minimum On Time tSYNC_MIN_ON 100 ns Minimum Off Time tSYNC_MIN_OFF 100 ns Input Clock High Voltage VH(SYNC) 1.3 V Input Clock Low Voltage VL(SYNC) 0.4 V SYNC Output Clock Frequency fCLK fSW kHz Positive Pulse Duty Cycle tCLK_PULSE_DUTY 50 % Rise or Fall Time tCLK_RISE_FALL 10 ns High Level Voltage VH(SYNC_OUT) VVREG V PRECISION ENABLING EN1, EN2, EN3, EN4 pins High Level Threshold VTH_H(EN) 0.811 0.835 V Low Level Threshold VTH_L(EN) 0.69 0.72 V Pull-Down Resistor RPULL-DOWN(EN) 2.0 MΩ POWER GOOD Internal Power-Good Rising Threshold VPWRGD(RISE) 86 91 96 % Internal Power-Good Hysteresis VPWRGD(HYS) 3.5 % Internal Power-Good Falling Delay tPWRGD_FALL 50 μs Rising Delay for PWRGD Pin tPWRGD_PIN_RISE 1 ms Leakage Current for PWRGD Pin IPWRGD_LEAKAGE 0.1 1 μA Output Low Voltage for PWRGD Pin VPWRGD_LOW 50 100 mV IPWRGD = 1 mA INTERNAL REGULATOR VDD Output Voltage VVDD 3.2 3.3 3.4 V IVDD = 10 mA VDD Current Limit ILIM_VDD 30 50 70 mA VREG Output Voltage VVREG 4.85 5.0 5.15 V IVREG = 50 mA Dropout Voltage VDROPOUT 225 mV IVREG = 50 mA VREG Current Limit ILIM_VREG 85 160 225 mA THERMAL SHUTDOWN Thermal Shutdown Threshold TSHDN 150 °C Thermal Shutdown Hysteresis THYS 15 °C Rev. G | Page 5 of 31 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGE INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK PULSE SKIP IN MAXIMUM DUTY SHORT-CIRCUIT PROTECTION (SCP) LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUIT FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE