Datasheet ADP5040 (Analog Devices) - 4

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ADP5040 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SW CHARACTERISTICS SW On Resistance RPFET PFET, AVIN = VIN1 = 3.6 V 180 240 mΩ PFET, AVIN = VIN1 = 5 V 140 190 mΩ RNFET NFET, AVIN = VIN1 = 3.6 V 170 235 mΩ NFET, AVIN = VIN1 = 5 V 150 210 mΩ Current Limit ILIMIT PFET switch peak current limit 1600 1950 2300 mA ACTIVE PULL-DOWN EN1 = 0 V 85 Ω OSCILLATOR FREQUENCY FOSC 2.5 3.0 3.5 MHz 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
LDO1, LDO2 SPECIFICATIONS
VIN2, VIN3 = (VOUT2, VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; AVIN, VIN1 ≥ VIN2, VIN3; CIN = 1 μF, COUT = 2.2 μF; TJ= −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1
Table 3. Parameter Symbol Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN2, VIN3 TJ = −40°C to +125°C 1.7 5.5 V OPERATING SUPPLY CURRENT Bias Current per LDO2 IVIN2BIAS /IVIN3BIAS IOUT3 = IOUT4 = 0 μA 10 30 μA IOUT2 = IOUT3 = 10 mA 60 100 μA IOUT2 = IOUT3 = 300 mA 165 245 μA Total System Input Current IIN Includes all current into AVIN, VIN1, VIN2 and VIN3 LDO1 or LDO2 Only IOUT2 = IOUT3 = 0 μA, all other channels disabled 53 μA LDO1 and LDO2 Only IOUT2 = IOUT3 = 0 μA, buck disabled 74 μA OUTPUT VOLTAGE ACCURACY VOUT2, VOUT3 100 μA < IOUT2 < 300 mA, 100 μA < IOUT3 < 300 mA −3 +3 % VIN2 = (VOUT2 + 0.5 V) to 5.5 V, VIN3 = (VOUT3 + 0.5 V) to 5.5 V REFERENCE VOLTAGE VFB2, VFB3 0.485 0.500 0.515 V REGULATION Line Regulation (ΔVOUT2/VOUT2)/ΔVIN2 VIN2 = (VOUT2 + 0.5 V) to 5.5 V −0.03 +0.03 %/ V (ΔVOUT3/VOUT3)/ΔVIN3 VIN3 = (VOUT3 + 0.5 V) to 5.5 V IOUT2 = IOUT3 = 1 mA Load Regulation3 (ΔVOUT2/VOUT2)/ΔIOUT2 IOUT2 = IOUT3 = 1 mA to 300 mA 0.002 0.0075 %/mA (ΔVOUT3/VOUT3)/ΔIOUT3 DROPOUT VOLTAGE4 VDROPOUT VOUT2 = VOUT3 = 5.0 V, IOUT2 = IOUT3 = 300 mA 72 mV VOUT2 = VOUT3 = 3.3 V, IOUT2 = IOUT3 = 300 mA 86 140 mV VOUT2 = VOUT3 = 2.5 V, IOUT2 = IOUT3 = 300 mA 107 mV VOUT2 = VOUT3 = 1.8 V, IOUT2 = IOUT3 = 300 mA 180 mV ACTIVE PULL-DOWN RPDLDO EN2/EN3 = 0 V 600 Ω CURRENT-LIMIT THRESHOLD5 ILIMIT TJ = −40°C to +125°C 335 470 mA OUTPUT NOISE OUTLDO2NOISE 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 123 μV rms 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 110 μV rms 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V 59 μV rms OUTLDO1NOISE 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V 140 μV rms 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V 129 μV rms 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V 66 μV rms Rev. D | Page 4 of 37 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS BUCK SPECIFICATIONS LDO1, LDO2 SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown Active Pull-Down BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Feedback Resistors Inductor Output Capacitor Input Capacitor LDO EXTERNAL COMPONENT SELECTION Feedback Resistors Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature APPLICATION DIAGRAM PCB LAYOUT GUIDELINES SUGGESTED LAYOUT BILL OF MATERIALS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE