Datasheet ADSP-BF504 (Analog Devices) - 4

ADSP-BF504
Each MAC can perform a 16-bit by 16-bit multiply in each The 40-bit shifter can perform shifts and rotates and is used cycle, accumulating the results into the 40-bit accumulators. to support normalization, field extract, and field deposit Signed and unsigned formats, rounding, and saturation instructions. are supported. The program sequencer controls the flow of instruction execu- The ALUs perform a traditional set of arithmetic and logical tion, including instruction alignment and decoding. For operations on 16-bit or 32-bit data. In addition, many special program flow control, the sequencer supports PC relative and instructions are included to accelerate various signal processing indirect conditional jumps (with static branch prediction), and tasks. These include bit operations such as field extract and pop- subroutine calls. Hardware is provided to support zero-over- ulation count, modulo 232 multiply, divide primitives, saturation head looping. The architecture is fully interlocked, meaning that and rounding, and sign/exponent detection. The set of video the programmer need not manage the pipeline when executing instructions include byte alignment and packing operations, instructions with data dependencies. 16-bit and 8-bit adds with clipping, 8-bit average operations, The address arithmetic unit provides two addresses for simulta- and 8-bit subtract/absolute value/accumulate (SAA) operations. neous dual fetches from memory. It contains a multiported Also provided are the compare/select and vector search register file consisting of four sets of 32-bit index, modify, instructions. length, and base registers (for circular buffering), and eight For certain instructions, two 16-bit ALU operations can be per- additional 32-bit pointer registers (for C-style indexed stack formed simultaneously on register pairs (a 16-bit high half and manipulation). 16-bit low half of a compute register). If the second ALU is used, quad 16-bit operations are possible.
ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 P3 DAG0 P2 DA1 32 P1 DA0 32 P0 Y 32 32 PREG RAB MEMOR O T SD 32 LD1 32 ASTAT 32 LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN 16 16 R4.H R4.L 8 8 8 8 R3.H R3.L DECODE R2.H R2.L R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER 40 40 A0 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core Rev. C | Page 4 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide