Datasheet ADSP-BF504 (Analog Devices) - 9

ADSP-BF504 DMA CONTROLLERS
If configured to generate a reset, the watchdog timer resets both the core and the processor peripherals. After a reset, software The processor has multiple, independent DMA channels that can determine whether the watchdog was the source of the support automated data transfers with minimal overhead for hardware reset by interrogating a status bit in the watchdog the processor core. DMA transfers can occur between the pro- timer control register. cessor’s internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished The timer is clocked by the system clock (SCLK) at a maximum between any of the DMA-capable peripherals and external frequency of fSCLK. devices connected to the external memory interface. DMA-
TIMERS
capable peripherals include the SPORTs, SPI ports, UARTs, RSI, and PPI. Each individual DMA-capable peripheral has at There are nine general-purpose programmable timer units in least one dedicated DMA channel. the processors. Eight timers have an external pin that can be The processor DMA controller supports both one-dimensional configured either as a pulse width modulator (PWM) or timer (1-D) and two-dimensional (2-D) DMA transfers. DMA trans- output, as an input to clock the timer, or as a mechanism for fer initialization can be implemented from registers or from sets measuring pulse widths and periods of external events. These of parameters called descriptor blocks. timers can be synchronized to an external clock input to the sev- eral other associated PF pins, to an external clock input to the The 2-D DMA capability supports arbitrary row and column PPI_CLK input pin, or to the internal SCLK. sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the The timer units can be used in conjunction with the two UARTs column step size can be less than the row step size, allowing to measure the width of the pulses in the data stream to provide implementation of interleaved data streams. This feature is a software auto-baud detect function for the respective serial especially useful in video applications where data can be channels. deinterleaved on the fly. The timers can generate interrupts to the processor core provid- Examples of DMA types supported by the processor DMA con- ing periodic events for synchronization, either to the system troller include: clock or to a count of external signals. • A single, linear buffer that stops upon completion In addition to the eight general-purpose programmable timers, a ninth timer is also provided. This extra timer is clocked by the • A circular, auto-refreshing buffer that interrupts on each internal processor clock and is typically used as a system tick full or fractionally full buffer clock for generation of operating system periodic interrupts. • 1-D or 2-D DMA using a linked list of descriptors
UP/DOWN COUNTERS AND
• 2-D DMA using an array o f descriptors, specifying only the
THUMBWHEEL INTERFACES
base DMA address within a common page Two 32-bit up/down counters are provided that can sense 2-bit In addition to the dedicated peripheral DMA channels, there are quadrature or binary codes as typically emitted by industrial two memory DMA channels, which are provided for transfers drives or manual thumbwheels. The counters can also operate between the various memories of the processor system with in general-purpose up/down count modes. Then, count direc- minimal processor intervention. Memory DMA transfers can be tion is either controlled by a level-sensitive input pin or by two controlled by a very flexible descriptor-based methodology or edge detectors. by a standard register-based autobuffer mechanism. A third counter input can provide flexible zero marker support
WATCHDOG TIMER
and can alternatively be used to input the push-button signal of The processor includes a 32-bit timer that can be used to imple- thumb wheels. All three pins have a programmable debouncing ment a software watchdog function. A software watchdog can circuit. improve system availability by forcing the processor to a known Internal signals forwarded to each timer unit enable these tim- state through generation of a core and system reset, nonmas- ers to measure the intervals between count events. Boundary kable interrupt (NMI), or general-purpose interrupt, if the registers enable auto-zero operation or simple system warning timer expires before being reset by software. The programmer by interrupts when programmable count values are exceeded. initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must
3-PHASE PWM UNITS
reload the counter before it counts to zero from the pro- The two/dual 3-phase PWM generation units each feature: grammed value. This protects the system from remaining in an unknown state where software, which would normally reset the • 16-bit center-based PWM generation unit timer, has stopped running due to an external noise condition • Programmable PWM pulse width or software error. • Single/double update modes • Programmable dead time and switching frequency • Twos-complemen t implementation which permits smooth transition to full ON and full OFF states Rev. C | Page 9 of 51 | June 2020 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table of Contents Revision History General Description Portable Low-Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory External (Interface-Accessible) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Up/Down Counters and Thumbwheel Interfaces 3-Phase PWM Units Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions RSI Interface Controller Area Network (CAN) Interface TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF504 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) ACM Interface Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF504 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Processor—Absolute Maximum Ratings ESD Sensitivity Processor—Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing RSI Controller Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing JTAG Test And Emulation Port Timing Processor—Output Drive Currents Processor—Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Processor—Environmental Conditions 88-Lead LFCSP Lead Assignment Outline Dimensions Ordering Guide