Datasheet A17700 (Allegro) - 19

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Pressure Sensor Interface and Signal Conditioning IC A17700 with Polynomial Signal Compensation and Advanced Diagnostics
In PWM output mode with dig_out_mode = 0, the device output activated through the EEPROM bit, VOUT is forced to a state as will hold the diagnostic state until the fault is removed or for a defined in Table 15. When VCC returns below VOVD(F), VOUT minimum of 5 ms to allow for appropriate detection. If PWM returns to its normal operating state after register read or report- carrier frequency was set to 500 Hz or lower, the fault state will ing flags through the output modes, which will clear the error be maintained for a minimum of 16 ms to allow for diagnostic flag. To avoid setting OVD by incidental supply flickering, enter- reporting for at least 2 cycles. ing the OVD state is suppressed for approximately 20 µs. The reporting priority in PWM mode with dig_out_mode = 0 In the case where OVD is disabled (EEPROM bit set to 0) but refers to the situation where multiple faults are detected at the MANCH_TRIGGER_DIS = 00 or 01 and output is in digital same time. In this case, only the fault with highest priority mode, an OVD event will bring the device to communication (i.e. number 1 is the highest) will be reported. mode and output will be forced to high impedance. In SENT output mode, depending on selected SENT configura- OVD threshold can be adjusted through EEPROM bit as per tion, the diagnostic flags can be reported through SCN bit 1, Table 16. through the short serial message, or through the SENT data nibble 4 and 5 (sent_data_cfg = 1). When fault is removed, the
Table 16: OVD Level Config
error flag register is cleared when the flag is transmitted through
OVD Falling
SENT message. Each of these three SENT reporting modes have
OVD_CFG OVD Rising Threshold (typ) (V) Threshold (typ) (V)
individual flag registers so that they can be cleared independently. 0 (Default) 5.8 5.6
DIAGNOSTIC DESCRIPTION
1 6.3 6.1 2 6.8 6.6
Undervoltage Detection (UVD)
3 6.8 6.6 The A17700 contains circuitry to continuously check if the supply voltage drops below the specified limit. Hysteresis is designed into
Overtemperature Detection (OTD)
the circuit to prevent chattering around the threshold. This hys- The OTD flag is set if the temperature sensor output saturates high, teresis is defined by VUVD(R) – VUVD(F). As an example, initially which indicates the ambient temperature is greater than 165°C VCC and VOUT are within the normal operating range. If VCC drops (default value). This assumes diagnostic reporting was activated below VUVD(F), and assuming this diagnostic is activated through through EEPROM bit. If this condition occurs, the OTD flag will the EEPROM bit, VOUT is forced to a state as defined in Table 15. be set and the device will go into a state as defined in Table 15. If When VCC returns above VUVD(R), VOUT returns to its normal oper- the temperature is detected to recover, a read of the device register ating state after register read or reporting flags through the output or reporting through the output modes will clear the error flag so modes, which will clear the error flag. If VCC drops below the normal operation can resume. The OTD error can be detected every internal reset level, VPOR(F), the output is forced to a high-imped- 8 ms and is never filtered. ance state. When VCC returns above the rising reset level, VPOR(R), the output responds with the UVD flag if enabled. To avoid setting
Undertemperature Detection (UTD)
UVD by incidental supply flickering, entering the UVD state is suppressed for approximately 20 µs. The UTD flag is set if the measured temperature is less than –70°C (default value). If this condition occurs, the UTD flag will be set
Overvoltage Detection (OVD)
and the device will go into a state as defined in Table 15. If the temperature is detected to recover, a read of the device register or The A17700 contains circuitry to continuously check if the sup- reporting through the output modes will clear the error flag so nor- ply voltage rises above the specified limit. Hysteresis is designed mal operation can resume. The UTD error can be detected every into the circuit to prevent chattering around the threshold. This 8 ms and is never filtered. hysteresis is defined by VOVD(R) – VOVD(F). As an example, initially VCC and VOUT are within the normal operating range. OTD and UTD thresholds can be adjusted through EEPROM bit If VCC rises above VOVD(R), and assuming this diagnostic is as per Table 17. 19 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Functional Block Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Pinout Diagram and Terminal List Operating Characteristics Functional Description Bandwidth Selection Output Response Time Power-On Time Front End Gain Adjustment Front End Differential Offset Adjustment Input Signal Range Calculation Fine Adjustment and Temperature Compensation Output Protocols Digital Output Mode Selection Digital Output Driver Fall Time Selection Broken Wire Detection Diagnostic Features Programming: Manchester Communication Entering Manchester Coding Manchester Interface Message Structure CRC Device Access Shadow Registers Device EEPROM and Register Access Lock EEPROM Map Volatile Registers Map Power Derating Package Outline Drawing