Datasheet SiC450, SiC451, SiC453 (Vishay) - 2
| Manufacturer | Vishay |
| Description | 4.5 V to 20 V Input, 15 A, 25 A, 40 A microBuck DC/DC Converter With PMBus Interface |
| Pages / Page | 48 / 2 — SiC450, SiC451, SiC453. PIN CONFIGURATION. Fig. 3 - Pin Configuration - … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
SiC450, SiC451, SiC453. PIN CONFIGURATION. Fig. 3 - Pin Configuration - Bottom View. PIN DESCRIPTION PIN NUMBER. SYMBOL
Model Line for this Datasheet
Text Version of Document
SiC450, SiC451, SiC453
www.vishay.com Vishay Siliconix
PIN CONFIGURATION
BOOT 6 A PV PV PV PH 4 G G NC 8 NC 9 ND IN IN IN H 5 1 2 3 7 10 NC 11 V PV 34 SEN- IN 12 V SEN+ P 33 13 P GND GOOD 14 ADDR 15 VSET P 32 16 A GND GND 17 RT / SYNC SW 31 18 SALRT 30 29 28 27 26 25 24 PV 23 V 22 V 21 EN 20 19 S S S S S G S S W W W W W L IN DD CL DA CC
Fig. 3 - Pin Configuration - Bottom View PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION
1, 2, 3, 34 PVIN Input voltage for power stage 4 PH Phase node, return path of high side gate driver 5 GH High side MOSFET gate monitor 6 BOOT Bootstrap voltage for high side gate driver (referenced to PH) 7, 16 AGND Analog signal return ground 8 NC Not used in Vishay device 9 NC Not used in Vishay device 10 NC Not used in Vishay device 11 VSEN- Remote sense amplifier negative input connect to output ground 12 VSEN+ Remote sense amplifier positive input connect to output Power good; open-drain output indicating V 13 P OUT is within set limits. Connect a pull up resistor typically GOOD 10 kΩ to VDD 14 ADDR PMBus address programming pin 15 VSET Output voltage set point by connecting a resistor from VSET to AGND Clock synchronization pin. Frequency can be set by connecting a resistor to A 17 RT/SYNC GND. Pending on master / salve configuration, a clock can be send / receive via the pin 18 SALRT PMBus alert. Connect to external host interface if desired 19 SDA PMBus data. Connect to external host interface 20 SCL PMBus clock. Connect to external host interface 21 EN Enable pin. Active high 5 V logic level input 22 VDD Internal 5 V circuits supply voltage. VDD is a LDO output, connect a 1 μF decoupling capacitor to AGND 23 VIN Internal driver supply voltage Supply voltage for internal gate drive. PV 24 PV CC is a LDO output. Connect a 4.7 μF decoupling capacitor to CC PGND 25 GL Low side MOSFET gate monitor 26 to 31 SW Switch node 32, 33 PGND Power ground. Common return for internal MOSFETs
ORDERING INFORMATION PART NUMBER PART MARKING MAXIMUM CURRENT PACKAGE
SiC450ED-T1-GE3 SiC450 40 A PowerPAK MLP34-57 SiC450EVB Reference board SiC451ED-T1-GE3 SiC451 25 A PowerPAK MLP34-57 SiC451EVB Reference board SiC453ED-T1-GE3 SiC453 15 A PowerPAK MLP34-57 SiC453EVB Reference board S21-0213-Rev. B, 08-Mar-2021
2
Document Number: 77863 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix
PIN CONFIGURATION
BOOT 6 A PV PV PV PH 4 G G NC 8 NC 9 ND IN IN IN H 5 1 2 3 7 10 NC 11 V PV 34 SEN- IN 12 V SEN+ P 33 13 P GND GOOD 14 ADDR 15 VSET P 32 16 A GND GND 17 RT / SYNC SW 31 18 SALRT 30 29 28 27 26 25 24 PV 23 V 22 V 21 EN 20 19 S S S S S G S S W W W W W L IN DD CL DA CC
Fig. 3 - Pin Configuration - Bottom View PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION
1, 2, 3, 34 PVIN Input voltage for power stage 4 PH Phase node, return path of high side gate driver 5 GH High side MOSFET gate monitor 6 BOOT Bootstrap voltage for high side gate driver (referenced to PH) 7, 16 AGND Analog signal return ground 8 NC Not used in Vishay device 9 NC Not used in Vishay device 10 NC Not used in Vishay device 11 VSEN- Remote sense amplifier negative input connect to output ground 12 VSEN+ Remote sense amplifier positive input connect to output Power good; open-drain output indicating V 13 P OUT is within set limits. Connect a pull up resistor typically GOOD 10 kΩ to VDD 14 ADDR PMBus address programming pin 15 VSET Output voltage set point by connecting a resistor from VSET to AGND Clock synchronization pin. Frequency can be set by connecting a resistor to A 17 RT/SYNC GND. Pending on master / salve configuration, a clock can be send / receive via the pin 18 SALRT PMBus alert. Connect to external host interface if desired 19 SDA PMBus data. Connect to external host interface 20 SCL PMBus clock. Connect to external host interface 21 EN Enable pin. Active high 5 V logic level input 22 VDD Internal 5 V circuits supply voltage. VDD is a LDO output, connect a 1 μF decoupling capacitor to AGND 23 VIN Internal driver supply voltage Supply voltage for internal gate drive. PV 24 PV CC is a LDO output. Connect a 4.7 μF decoupling capacitor to CC PGND 25 GL Low side MOSFET gate monitor 26 to 31 SW Switch node 32, 33 PGND Power ground. Common return for internal MOSFETs
ORDERING INFORMATION PART NUMBER PART MARKING MAXIMUM CURRENT PACKAGE
SiC450ED-T1-GE3 SiC450 40 A PowerPAK MLP34-57 SiC450EVB Reference board SiC451ED-T1-GE3 SiC451 25 A PowerPAK MLP34-57 SiC451EVB Reference board SiC453ED-T1-GE3 SiC453 15 A PowerPAK MLP34-57 SiC453EVB Reference board S21-0213-Rev. B, 08-Mar-2021
2
Document Number: 77863 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
