Datasheet MAX17270, MAX17271 (Maxim) - 8
| Manufacturer | Maxim |
| Description | nanoPower Triple-Output, Single-Inductor, Multiple-Output (SIMO) Buck-Boost Regulator |
| Pages / Page | 37 / 8 — Electrical Characteristics - I2C. PARAMETER. SYMBOL. CONDITIONS. MIN. … |
| File Format / Size | PDF / 2.0 Mb |
| Document Language | English |
Electrical Characteristics - I2C. PARAMETER. SYMBOL. CONDITIONS. MIN. TYP. MAX. UNITS. POWER SUPPLY. SDA AND SCL I/O STAGE
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MAX17270/MAX17271 nanoPower Triple-Output, Single-Inductor, Multiple-Output (SIMO) Buck-Boost Regulator
Electrical Characteristics - I2C
(VVPWR = VVSUP = 3.7V, VIO = 1.8V, limits are 100% production tested at TJ = +25°C, limits over the operating temperature range (TJ = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY
VIO Voltage Range VIO VIO ≤ VSUP 1.7 1.8 3.6 V VIO = 3.6V, VSDA = VSCL = 0V or 3.6V, VIO Bias Current TA = +25°C -1 0 +1 μA VIO = 1.7V, VSDA = VSCL= 0V or 1.7V 0 +1
SDA AND SCL I/O STAGE
SCL, SDA Input High Voltage VIH VIO = 1.7V to 3.6V 0.7 x V V IO SCL, SDA Input Low Voltage VIL VIO = 1.7V to 3.6V 0.3 x V V IO SCL, SDA Input Hysteresis V 0.05 x HYS V V IO SCL, SDA Input Leakage Current II VIO = 3.6V, VSCL = VSDA = 0V and 3.6V -10 +10 μA SDA Output Low Voltage VOL Sinking 20mA 0.4 V SCL, SDA Pin Capacitance CI 10 pF
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST-MODE PLUS) (Note 2)
Clock Frequency fSCL 0 1000 kHz Hold Time (REPEATED) START Condition tHD_STA 0.26 μs SCL Low Period tLOW 0.5 μs SCL High Period tHIGH 0.26 μs Setup Time (REPEATED) START Condition tSU_STA 0.26 μs Data Hold Time tHD_DAT 0 μs Data Setup Time tSU_DAT 50 ns Setup Time for STOP Condition tSU_STO 0.26 μs Bus Free Time between STOP and START Condition tBUF 0.5 μs Pulse Width of Suppressed Maximum pulse width of spikes that must Spikes tSP be suppressed by the input filter 50 ns
Note 1:
Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through correlation using statistical quality control methods.
Note 2:
Design guidance only. Not production tested. www.maximintegrated.com Maxim Integrated │ 8
Electrical Characteristics - I2C
(VVPWR = VVSUP = 3.7V, VIO = 1.8V, limits are 100% production tested at TJ = +25°C, limits over the operating temperature range (TJ = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY
VIO Voltage Range VIO VIO ≤ VSUP 1.7 1.8 3.6 V VIO = 3.6V, VSDA = VSCL = 0V or 3.6V, VIO Bias Current TA = +25°C -1 0 +1 μA VIO = 1.7V, VSDA = VSCL= 0V or 1.7V 0 +1
SDA AND SCL I/O STAGE
SCL, SDA Input High Voltage VIH VIO = 1.7V to 3.6V 0.7 x V V IO SCL, SDA Input Low Voltage VIL VIO = 1.7V to 3.6V 0.3 x V V IO SCL, SDA Input Hysteresis V 0.05 x HYS V V IO SCL, SDA Input Leakage Current II VIO = 3.6V, VSCL = VSDA = 0V and 3.6V -10 +10 μA SDA Output Low Voltage VOL Sinking 20mA 0.4 V SCL, SDA Pin Capacitance CI 10 pF
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST-MODE PLUS) (Note 2)
Clock Frequency fSCL 0 1000 kHz Hold Time (REPEATED) START Condition tHD_STA 0.26 μs SCL Low Period tLOW 0.5 μs SCL High Period tHIGH 0.26 μs Setup Time (REPEATED) START Condition tSU_STA 0.26 μs Data Hold Time tHD_DAT 0 μs Data Setup Time tSU_DAT 50 ns Setup Time for STOP Condition tSU_STO 0.26 μs Bus Free Time between STOP and START Condition tBUF 0.5 μs Pulse Width of Suppressed Maximum pulse width of spikes that must Spikes tSP be suppressed by the input filter 50 ns
Note 1:
Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through correlation using statistical quality control methods.
Note 2:
Design guidance only. Not production tested. www.maximintegrated.com Maxim Integrated │ 8
