Datasheet LM25149-Q1 (Texas Instruments) - 4
| Manufacturer | Texas Instruments |
| Description | 42-V Automotive Synchronous Buck DC/DC Controller with Ultra-Low IQ and Integrated Active EMI Filter |
| Pages / Page | 51 / 4 — LM25149-Q1. www.ti.com. Table 6-1. Pin Functions (continued). PIN. … |
| File Format / Size | PDF / 4.1 Mb |
| Document Language | English |
LM25149-Q1. www.ti.com. Table 6-1. Pin Functions (continued). PIN. I/O(1). DESCRIPTION. NO. NAME. NCE INFO. R MA. 6.1 Wettable Flanks. TION
Model Line for this Datasheet
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LM25149-Q1
SNVSBV6 – DECEMBER 2020
www.ti.com Table 6-1. Pin Functions (continued) PIN I/O(1) DESCRIPTION NO. NAME
13 HO O High-side gate driver turnon output Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the high- 14 SW P side MOSFET, and the drain terminal of the low-side MOSFET. 15 CBOOT P High-side driver supply for bootstrap gate drive Optional input for an external bias supply. If V 16 VCCX P VCCX > 4.3 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. 17 PG P An open-collector output that goes low if VOUT is outside the specified regulation window Connect PFM to AGND to enable diode emulation mode. Connect PFM to VDDA to operate the LM5149- 18 PFM/SYNC I Q1 in forced PWM (FPWM) mode with continuous conduction at light loads. PFM can also be used as a synchronization input to synchronize the internal oscillator to an external clock.
AD
An active-high input (V 19 EN I EN 1) enables the output. If the output is not enabled, the LM5149-Q1 is in shutdown mode.
V
Current sense amplifier input. Connect the ISNS+ to the inductor side of the external current sense resistor
A
20 ISNS+ I (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin connection.
NCE INFO
Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the current 21 VOUT I sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used). 22 AEFVDDA P Active EMI bias power. Connect a ceramic capacitor between AEFVDDA and AVSS. 23 SENSE I Active EMI sense input 24 REFAGND G Active EMI reference ground (1) P = Power, G = Ground, I = Input, O = Output.
R MA 6.1 Wettable Flanks
100% automated visual inspection (AVI) post-assembly is typically required to meet reliability and robustness
TION
standards. Standard quad-flat no-lead (QFN) packages do not have solderable or exposed pins and terminals that are easily viewed. It is therefore difficult to visually determine whether or not the package is successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve the issue of side-lead wetting of leadless packaging. The LM25149-Q1 is assembled using a 24-pin VQFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs. 4 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM25149-Q1 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Description (continued) 6 Pin Configuration and Functions 6.1 Wettable Flanks 7 Specifications 7.1 Absolute Maximum Ratings 7.2 ESD Ratings 7.3 Recommended Operating Conditions 7.4 Thermal Information 7.5 Electrical Characteristics 7.6 Active EMI Filter 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Input Voltage Range (VIN) 8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA) 8.3.3 Enable (EN) 8.3.4 Power Good Monitor (PG) 8.3.5 Switching Frequency (RT) 8.3.6 Active EMI Filter 8.3.7 Dual Random Spread Spectrum (DRSS) 8.3.8 Soft-Start 8.3.9 Output Voltage Setpoint (FB) 8.3.10 Minimum Controllable On-Time 8.3.11 Error Amplifier and PWM Comparator (FB, EXTCOMP) 8.3.12 Slope Compensation 8.3.13 Inductor Current Sense (ISNS+, VOUT) 8.3.13.1 Shunt Current Sensing 8.3.13.2 Inductor DCR Current Sensing 8.3.14 Hiccup Mode Current Limiting 8.3.15 High-Side and Low-Side Gate Drivers (HO, LO) 8.3.16 Output Configurations (CNFG) 8.3.17 Single-Output Two-phase Operation 8.4 Device Functional Modes 8.4.1 Standby Modes 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC) 8.4.3 Thermal Shutdown 9 Application and Implementation 9.1 Application Information 9.1.1 Power Train Components 9.1.1.1 Buck Inductor 9.1.1.2 Output Capacitors 9.1.1.3 Input Capacitors 9.1.1.4 Power MOSFETs 9.1.1.5 EMI Filter 9.1.2 Error Amplifier and Compensation 9.2 Typical Application 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.2.1 Custom Design With WEBENCH® Tools 9.2.2.2 Custom Design With Excel Quickstart Tool 9.2.2.3 Buck Inductor 9.2.2.4 Current-Sense Resistance 9.2.2.5 Output Capacitors 9.2.2.6 Input Capacitors 9.2.2.7 Frequency Set Resistor 9.2.2.8 Feedback Resistors 9.2.2.9 Compensation Components 9.2.2.10 Active EMI Components 9.2.3 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.1.1 Power Stage Layout 11.1.2 Gate-Drive Layout 11.1.3 PWM Controller Layout 11.1.4 Active EMI Layout 11.1.5 Thermal Design and Layout 11.1.6 Ground Plane Design 11.2 Layout Example 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.2 Custom Design With WEBENCH® Tools 12.2 Documentation Support 12.2.1 Related Documentation 12.2.1.1 PCB Layout Resources 12.2.1.2 Thermal Design Resources 12.3 Receiving Notification of Documentation Updates 12.4 Support Resources 12.5 Trademarks 12.6 Electrostatic Discharge Caution 12.7 Glossary 13 Mechanical, Packaging, and Orderable Information
LM25149-Q1
SNVSBV6 – DECEMBER 2020
www.ti.com Table 6-1. Pin Functions (continued) PIN I/O(1) DESCRIPTION NO. NAME
13 HO O High-side gate driver turnon output Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the high- 14 SW P side MOSFET, and the drain terminal of the low-side MOSFET. 15 CBOOT P High-side driver supply for bootstrap gate drive Optional input for an external bias supply. If V 16 VCCX P VCCX > 4.3 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. 17 PG P An open-collector output that goes low if VOUT is outside the specified regulation window Connect PFM to AGND to enable diode emulation mode. Connect PFM to VDDA to operate the LM5149- 18 PFM/SYNC I Q1 in forced PWM (FPWM) mode with continuous conduction at light loads. PFM can also be used as a synchronization input to synchronize the internal oscillator to an external clock.
AD
An active-high input (V 19 EN I EN 1) enables the output. If the output is not enabled, the LM5149-Q1 is in shutdown mode.
V
Current sense amplifier input. Connect the ISNS+ to the inductor side of the external current sense resistor
A
20 ISNS+ I (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin connection.
NCE INFO
Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the current 21 VOUT I sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used). 22 AEFVDDA P Active EMI bias power. Connect a ceramic capacitor between AEFVDDA and AVSS. 23 SENSE I Active EMI sense input 24 REFAGND G Active EMI reference ground (1) P = Power, G = Ground, I = Input, O = Output.
R MA 6.1 Wettable Flanks
100% automated visual inspection (AVI) post-assembly is typically required to meet reliability and robustness
TION
standards. Standard quad-flat no-lead (QFN) packages do not have solderable or exposed pins and terminals that are easily viewed. It is therefore difficult to visually determine whether or not the package is successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to resolve the issue of side-lead wetting of leadless packaging. The LM25149-Q1 is assembled using a 24-pin VQFN package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and manufacturing costs. 4 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: LM25149-Q1 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Description (continued) 6 Pin Configuration and Functions 6.1 Wettable Flanks 7 Specifications 7.1 Absolute Maximum Ratings 7.2 ESD Ratings 7.3 Recommended Operating Conditions 7.4 Thermal Information 7.5 Electrical Characteristics 7.6 Active EMI Filter 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Input Voltage Range (VIN) 8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA) 8.3.3 Enable (EN) 8.3.4 Power Good Monitor (PG) 8.3.5 Switching Frequency (RT) 8.3.6 Active EMI Filter 8.3.7 Dual Random Spread Spectrum (DRSS) 8.3.8 Soft-Start 8.3.9 Output Voltage Setpoint (FB) 8.3.10 Minimum Controllable On-Time 8.3.11 Error Amplifier and PWM Comparator (FB, EXTCOMP) 8.3.12 Slope Compensation 8.3.13 Inductor Current Sense (ISNS+, VOUT) 8.3.13.1 Shunt Current Sensing 8.3.13.2 Inductor DCR Current Sensing 8.3.14 Hiccup Mode Current Limiting 8.3.15 High-Side and Low-Side Gate Drivers (HO, LO) 8.3.16 Output Configurations (CNFG) 8.3.17 Single-Output Two-phase Operation 8.4 Device Functional Modes 8.4.1 Standby Modes 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC) 8.4.3 Thermal Shutdown 9 Application and Implementation 9.1 Application Information 9.1.1 Power Train Components 9.1.1.1 Buck Inductor 9.1.1.2 Output Capacitors 9.1.1.3 Input Capacitors 9.1.1.4 Power MOSFETs 9.1.1.5 EMI Filter 9.1.2 Error Amplifier and Compensation 9.2 Typical Application 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.2.1 Custom Design With WEBENCH® Tools 9.2.2.2 Custom Design With Excel Quickstart Tool 9.2.2.3 Buck Inductor 9.2.2.4 Current-Sense Resistance 9.2.2.5 Output Capacitors 9.2.2.6 Input Capacitors 9.2.2.7 Frequency Set Resistor 9.2.2.8 Feedback Resistors 9.2.2.9 Compensation Components 9.2.2.10 Active EMI Components 9.2.3 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.1.1 Power Stage Layout 11.1.2 Gate-Drive Layout 11.1.3 PWM Controller Layout 11.1.4 Active EMI Layout 11.1.5 Thermal Design and Layout 11.1.6 Ground Plane Design 11.2 Layout Example 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.2 Custom Design With WEBENCH® Tools 12.2 Documentation Support 12.2.1 Related Documentation 12.2.1.1 PCB Layout Resources 12.2.1.2 Thermal Design Resources 12.3 Receiving Notification of Documentation Updates 12.4 Support Resources 12.5 Trademarks 12.6 Electrostatic Discharge Caution 12.7 Glossary 13 Mechanical, Packaging, and Orderable Information
