Datasheet 1EDBx275F (Infineon) - 6

link to page 6 link to page 7 link to page 6
EiceDRIVER™ 1EDBx275F Single-channel isolated gate-driver ICs in 150 mil DSO package Functional description 2.2.2 Output supply voltage
The output die is powered via VDDO (up to 20 V). A ceramic bypass capacitor must be placed between VDDO and GNDO in close proximity to the device. A minimum capacitance of 20 x Ciss (MOSFET input capacitance) is recommended to ensure an acceptable ripple (5% of VDDO) on the supply pin. The minimum supply voltage is set by the Undervoltage Lockout (UVLO) function. The gate-driver output can be switched only, if the output supply voltage (VDDO) exceeds the output-side UVLO. Thus it can be guaranteed that the switch transistor is not operated, if the driving voltage is too low to achieve a complete and fast transition to the "on" state. Low driving voltage in fact could cause the power MOSFET to enter its saturation (ohmic) region with potentially destructive power dissipation; the output UVLO ensures that the switch transistor always stays within its Safe Operating Area (SOA). Versions with 4 V, 8 V, 12 V, 15 V UVLO thresholds for the output supply are currently available;
Table 3
shows the recommended UVLO levels for different Infineon power switch families.
Table 3 Recommended 1EDBx275F UVLO levels for typical use-cases Switch family Switch part number example Recommended 1EDBx275F
Logic level OptiMOSTM BSC010N04LS6, BSZ070N08LS5, .. 1EDB7275F (4 V UVLO) Normal level OptiMOSTM BSC040N10NS5, BSZ084N08NS5, .. 1EDB8275F (8 V UVLO) CoolMOSTM IPP60R099C7, IPB60R600P6, .. 1EDB8275F (8 V UVLO) 650 V CoolSiCTM IMZA65R027M1H, IMW65R107M1H, .. 1EDB6275F (12 V UVLO for 15V VGS driving) 1EDB9275F (15 V UVLO for 18V VGS driving) 600 V CoolGaNTM IGOT60R070D1, IGLD60R070D1, .. 1EDB7275F (4V UVLO)
2.2.3 Input stage
The logic driver output state is equal to the non-inverted or inverted input signal state at pins IN+ or IN-, respectively. The non-inverting input IN+ is internally pulled down to a logic low voltage and the inverting input is internally pulled up to a logic high voltage. This prevents any switching-on during power-up or in other situations with insufficient supply voltage. The input is compatible with LV-TTL levels and provide a hysteresis of typically 0.9 V. This hysteresis is independent of the supply voltage VDDI.
Table 4
shows the IN+, IN- driver logic in case of sufficiently high supply voltage. Otherwise the outputs of the driver are determined by the Undervoltage Lockout (UVLO) and Output Active Clamping functionalities as shown in
Table 5
.
Table 4 Logic table in case of sufficient bias power Inputs Supplies Outputs Note IN+ IN- V DDI, V DDO OUT
H L H – x H >UVLOVDDx,on (active) L The output is disabled via IN- (active low) L x L The output is disabled via IN+ (active high)
2.3 Driver output
The rail-to-rail output stage realized with complementary MOS transistors is able to provide a typical 5.4 A sourcing and 9.8 A sinking peak current for a 15 V supply. The low on-resistance coming together with high driving current is particularly beneficial for fast switching of very large MOSFETs. With a Ron of 0.95 Ω for the sourcing pMOS and 0.48 Ω for the sinking nMOS transistor the driver can in most applications be considered as a nearly Final Data Sheet 6 Rev. 2.1 2021-04-21 Document Outline Description Table of Contents 1 Pin configuration and description 2 Functional description 2.1 Block diagram 2.2 Power supply and Undervoltage Lockout (UVLO) 2.2.1 Input supply voltage 2.2.2 Output supply voltage 2.2.3 Input stage 2.3 Driver output 2.4 Output active clamping 2.5 CT communication and input to output data transmission 3 Electrical characteristics and parameters 3.1 Absolute maximum ratings 3.2 Thermal characteristics 3.3 Operating range 3.4 Electrical characteristics 3.5 Isolation specifications 4 Timing diagrams 5 Layout recommendation 6 Application notes 6.1 Driving 600 V CoolGaNTM 6.2 Driving 650 V CoolSiCTM 7 Typical characteristics 8 Package outline dimensions 8.1 Device numbers and markings 8.2 Package PG-DSO-8 Revision history