Datasheet TMP114 (Texas Instruments) - 9

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TMP114 www.ti.com
SNIS214 – JUNE 2021
7.3 Feature Description 7.3.1 Cyclic Redundancy Check (CRC)
The TMP114 implements an optional CRC function to improve data integrity and communication robustness using an 8-bit polynomial that is checked during communication. By default the feature is disabled and can be enabled by setting the CRC_EN bit in the Configuration register. When enabled, the CRC function starts with the seed value of FFh at every start or repeated start condition on the bus and computes one CRC value. After transmitting or receiving a CRC value the TMP114, the next CRC will have the seed value reset to FFh. When the TMP114 operates in target receive mode or during a write bus transaction, the CRC byte covers the device address, pointer address, and received data bytes. If the device detects a CRC error on the byte, it shall set the CRC_flag status bit in the Alert_Status register. If the CRC byte is not present, the transaction is discarded and the CRC flag is not set. When the TMP114 operates in target transmit mode or during a read bus transaction, the CRC byte covers the device address and the sent data bytes.
TION 7.3.2 Temperature Limits
TMP114 includes an on-board temperature limit warning. At the end of every completed conversion, the TMP114
MA
compares the result against the limits stored in the low limit register and the high limit register. When the
R
results exceed the THigh_Limit register value, the THigh_Status and THigh_Flag bits are set. Upon read, the THigh_Flag will clear but the THigh_Status bit will remain set. After the measured temperature crosses below the THigh_Limit - THigh_Hyst value, the THigh_Status bit will clear and the THigh_Flag bit is set again to indicate a change in the temperature with respect to the limits. If the device is unable to read the Temp_Result register for a prolonged period of time, the flag bits can be used to determine if a thermal limit was crossed during that time. The flag bits will only clear after a successful Alert_Status register read, therefore the high and low flags can help determine if the system crossed the
NCE INFO
thermal limit before an I2C read could be performed. The Status bits will automatically update with changing
A
Temp_Result values. Figure 7-1 depicts this behavior.
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Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TMP114 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 I2C Interface Timing 6.7 Two-Wire Timing Diagram 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Cyclic Redundancy Check (CRC) 7.3.2 Temperature Limits 7.3.3 Slew Rate Warning 7.3.4 NIST Traceability 7.4 Device Functional Modes 7.4.1 Continuous Conversion Mode 7.4.2 Shutdown Mode 7.4.2.1 One-Shot Temperature Conversions 7.5 Programming 7.5.1 Temperature Data Format 7.5.2 I2C and SMBus Interface 7.5.3 Device Address 7.5.4 Bus Transactions 7.5.4.1 Auto-Increment 7.5.4.2 Writes 7.5.4.2.1 CRC Enabled Writes 7.5.4.3 Reads 7.5.4.3.1 CRC Enabled Reads 7.5.4.4 General Call Reset Function 7.5.4.5 Time-Out Function 7.5.4.6 I2C in I3C Mixed Fast Mode 7.5.4.7 Cyclic Redundancy Check Implementation 7.6 Register Map 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates 11.2 Support Resources 11.3 Trademarks 11.4 Electrostatic Discharge Caution 11.5 Glossary 12 Mechanical, Packaging, and Orderable Information 12.1 Tape and Reel Information