Datasheet ALED6000 (STMicroelectronics) - 4
| Manufacturer | STMicroelectronics |
| Description | Automotive 3 A 61 V monolithic current source with dimming capability |
| Pages / Page | 45 / 4 — ALED6000. Pin settings. 3.1. Pin connection. Figure 3. Pin connection … |
| File Format / Size | PDF / 3.4 Mb |
| Document Language | English |
ALED6000. Pin settings. 3.1. Pin connection. Figure 3. Pin connection (top view). 3.2. Pin description. Table 1. Pin description. Pin
Model Line for this Datasheet
Text Version of Document
ALED6000 Pin settings 3 Pin settings 3.1 Pin connection Figure 3. Pin connection (top view)
VBIAS 1 16 GND VIN 2 15 BOOT VIN 3 14 LX VCC 4 EXPOSED 13 LX PAD TO EN 5 SGND 12 DIM SS 6 11 ILIM SYNCH 7 10 FSW COMP 8 9 FB
3.2 Pin description Table 1. Pin description # Pin Description
Auxiliary input that can be used to supply part of the analog circuitry to increase the efficiency at light load. 1 VBIAS Connect to GND if not used or bypass with a 1 µF ceramic capacitor if supplied by an auxiliary rail 2 VIN DC input voltage 3 VIN DC input voltage Filtered DC input voltage to the internal 4 VCC circuitry. Bypass to the signal GND by a 1 µF ceramic capacitor Active high enable pin. Connect to VCC 5 EN pin if not used An internal current generator (5 µA 6 SS typ.) charges the external capacitor to implement the soft-start 7 SYNCH Master / slave synchronization Output of the error amplifier. The 8 COMP designed compensation network is connected on this pin 9 FB Inverting input of the error amplifier A pull-down resistor to GND selects the 10 FSW switching frequency
DS13018
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Rev 2 page 4/45
Document Outline Cover image Features Applications Description 1 Application schematic 2 Block diagram 3 Pin settings 3.1 Pin connection 3.2 Pin description 3.3 Maximum ratings 3.4 Thermal data 3.5 ESD protection 4 Electrical characteristics 5 Functional description 5.1 Oscillator and synchronization 5.2 Soft-start 5.3 Digital dimming 5.4 Error amplifier and light-load management 5.5 Low VIN operation 5.6 Overcurrent protection 5.7 Overtemperature protection 6 Application information 6.1 Input capacitor selection 6.2 Output capacitor and inductor selection 6.3 Compensation strategy 6.4 Thermal considerations 6.5 Layout considerations 7 Demonstration board 8 Application notes – alternative topologies 8.1 Inverting buck-boost 8.2 Positive buck-boost 8.3 Floating boost 8.4 Compensation strategy for alternative topologies 9 Package information 9.1 HTSSOP16 package information Revision history
VBIAS 1 16 GND VIN 2 15 BOOT VIN 3 14 LX VCC 4 EXPOSED 13 LX PAD TO EN 5 SGND 12 DIM SS 6 11 ILIM SYNCH 7 10 FSW COMP 8 9 FB
3.2 Pin description Table 1. Pin description # Pin Description
Auxiliary input that can be used to supply part of the analog circuitry to increase the efficiency at light load. 1 VBIAS Connect to GND if not used or bypass with a 1 µF ceramic capacitor if supplied by an auxiliary rail 2 VIN DC input voltage 3 VIN DC input voltage Filtered DC input voltage to the internal 4 VCC circuitry. Bypass to the signal GND by a 1 µF ceramic capacitor Active high enable pin. Connect to VCC 5 EN pin if not used An internal current generator (5 µA 6 SS typ.) charges the external capacitor to implement the soft-start 7 SYNCH Master / slave synchronization Output of the error amplifier. The 8 COMP designed compensation network is connected on this pin 9 FB Inverting input of the error amplifier A pull-down resistor to GND selects the 10 FSW switching frequency
DS13018
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Rev 2 page 4/45
Document Outline Cover image Features Applications Description 1 Application schematic 2 Block diagram 3 Pin settings 3.1 Pin connection 3.2 Pin description 3.3 Maximum ratings 3.4 Thermal data 3.5 ESD protection 4 Electrical characteristics 5 Functional description 5.1 Oscillator and synchronization 5.2 Soft-start 5.3 Digital dimming 5.4 Error amplifier and light-load management 5.5 Low VIN operation 5.6 Overcurrent protection 5.7 Overtemperature protection 6 Application information 6.1 Input capacitor selection 6.2 Output capacitor and inductor selection 6.3 Compensation strategy 6.4 Thermal considerations 6.5 Layout considerations 7 Demonstration board 8 Application notes – alternative topologies 8.1 Inverting buck-boost 8.2 Positive buck-boost 8.3 Floating boost 8.4 Compensation strategy for alternative topologies 9 Package information 9.1 HTSSOP16 package information Revision history
