Datasheet CYW43455 (Cypress) - 2
| Manufacturer | Cypress |
| Description | Single-Chip 5G WiFi IEEE 802.11n/ac MAC/ Baseband/ Radio with Integrated Bluetooth 5.0 |
| Pages / Page | 121 / 2 — CYW43455. Cypress Part Numbering Scheme. Table 1. Mapping Table for Part … |
| File Format / Size | PDF / 2.7 Mb |
| Document Language | English |
CYW43455. Cypress Part Numbering Scheme. Table 1. Mapping Table for Part Number between Broadcom and Cypress
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CYW43455
Single-Chip 5G WiFi IEEE 802.11n/ac MAC/ Baseband/ Radio with Integrated Bluetooth 5.0 The Cypress CYW43455 single-chip device provides the highest level of integration for Internet of Things applications and handheld wireless system with integrated single-stream IEEE 802.11ac MAC/baseband/radio and, Bluetooth 5.0. In IEEE 802.11ac mode, the WLAN operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz channels for data rates of up to 433.3 Mbps. All rates specified in the IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz and 5 GHz transmit amplifiers and receive low-noise amplifiers. Optional external PAs and LNAs are also supported. The WLAN section supports the following host interface options: an SDIO v3.0 interface that can operate in 4b or 1b mode, a high-speed 4-wire UART, and a PCIe1Gen1 (3.0 compliant) interface. The Bluetooth section supports a high-speed 4-wire UART interface. Using advanced design techniques and process technology to reduce active and idle power, the CYW43455 is designed to address the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which simplifies the system power topology and allows for direct operation from a mobile platform battery while maximizing battery life. The CYW43455 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external radios (such as LTE cellular and GPS) is provided via an external interface. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number
BCM43455 CYW43455 BCM43455XKUBG CYW43455XKUBG BCM43455HKUBG CYW43455HKUBG BCM4329 CYW4329 BCM4330 CYW4330
Features IEEE 802.11x Key Features
■ IEEE 802.11ac compliant. ■ Support for optional front-end modules (FEM) with external PAs and LNAs. ■ Support for TurboQAM® (MCS0–MCS8 86 Mbps and MCS0– MCS9 96 Mbps) HT20, 20 MHz channel bandwidth. ■ Supports optional integrated T/R switch for 2.4 GHz band. ■ Single-stream spatial multiplexing up to 433.3 Mbps data rate. ■ Supports RF front-end architecture with a single dual-band antenna shared between Bluetooth and WLAN for lowest ■ Supports 20, 40, and 80 MHz channels with optional SGI (256 QAM modulation). system cost. ■ Shared Bluetooth and WLAN receive signal path eliminates the ■ Full IEEE 802.11a/b/g/n legacy compatibility with enhanced need for an external power splitter while maintaining excellent performance. sensitivity for both Bluetooth and WLAN. ■ Supports explicit IEEE 802.11ac transmit beamforming. ■ Internal fractional-n PLL allows support for a wide range of ■ TX and RX low-density parity check (LDPC) support for reference clock frequencies. improved range and power efficiency. ■ Supports IEEE 802.15.2 external coexistence interface to ■ On-chip power amplifiers and low-noise amplifiers for both optimize bandwidth utilization with other co-located wireless bands. technologies such as LTE or GPS. 1. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-15051 Rev. *O Revised March 22, 2019 Document Outline 1. CYW43455 Overview 1.1 Overview 1.2 Standards Compliance 2. Power Supplies and Power Management 2.1 Power Supply Topology 2.2 CYW43455 PMU Features 2.3 WLAN Power Management 2.4 PMU Sequencing Each resource is in one of four states: 2.5 Power-Off Shutdown 2.6 Power-Up/Power-Down/Reset Circuits 3. Frequency References 3.1 Crystal Interface and Clock Generation 3.2 External Frequency Reference 3.3 Frequency Selection 3.4 External 32.768 kHz Low-Power Oscillator 4. Bluetooth Subsystem Overview 4.1 Features 4.2 Bluetooth Radio 4.2.1 Transmit 4.2.2 Digital Modulator 4.2.3 Digital Demodulator and Bit Synchronizer 4.2.4 Power Amplifier 4.2.5 Receiver 4.2.6 Digital Demodulator and Bit Synchronizer 4.2.7 Receiver Signal Strength Indicator 4.2.8 Local Oscillator Generation 4.2.9 Calibration 5. Bluetooth Baseband Core 5.1 Bluetooth 4.0 Features 5.2 Bluetooth 4.2 Features 5.3 Bluetooth Low Energy 5.4 Bluetooth 5.0 5.5 Link Control Layer 5.6 Test Mode Support 5.7 Bluetooth Power Management Unit 5.7.1 RF Power Management 5.7.2 Host Controller Power Management 5.7.3 BBC Power Management 5.8 Adaptive Frequency Hopping 5.9 Advanced Bluetooth/WLAN Coexistence 5.10 Fast Connection (Interlaced Page and Inquiry Scans) 6. Microprocessor and Memory Unit for Bluetooth 6.1 RAM, ROM, and Patch Memory 6.2 Reset 7. Bluetooth Peripheral Transport Unit 7.1 SPI Interface 7.2 SPI/UART Transport Detection 7.3 PCM Interface 7.3.1 Slot Mapping 7.3.2 Frame Synchronization 7.3.3 Data Formatting 7.3.4 Wideband Speech Support 7.3.5 Multiplexed Bluetooth Over PCM 7.3.6 Burst PCM Mode 7.3.7 PCM Interface Timing 7.4 UART Interface 7.5 I2S Interface 7.5.1 I2S Timing 8. WLAN Global Functions 8.1 WLAN CPU and Memory Subsystem 8.2 One-Time Programmable Memory 8.3 GPIO Interface 8.4 External Coexistence Interface 8.5 UART Interface 8.6 JTAG/SWD Interface 9. WLAN Host Interfaces 9.1 SDIO v3.0 9.2 SDIO Pins 9.3 PCI Express Interface 9.4 Transaction Layer Interface 9.4.1 Data Link Layer 9.4.2 Physical Layer 9.4.3 Logical Subblock 9.4.4 Scrambler/Descrambler 9.4.5 8B/10B Encoder/Decoder 9.4.6 Elastic FIFO 9.4.7 Electrical Subblock 9.4.8 Configuration Space 10. Wireless LAN MAC and PHY 10.1 IEEE 802.11ac MAC 10.1.1 PSM 10.1.2 WEP 10.1.3 TXE 10.1.4 RXE 10.1.5 IFS 10.1.6 TSF 10.1.7 NAV 10.1.8 MAC-PHY Interface 10.2 IEEE 802.11ac PHY 11. WLAN Radio Subsystem 11.1 Receiver Path 11.2 Transmit Path 11.3 Calibration 12. Ball Map and Pin Descriptions 12.1 Ball Map 12.2 Pin List by Pin Number 12.3 Pin List by Pin Name 12.4 Pin Descriptions 12.5 WLAN GPIO Signals and Strapping Options 12.5.1 Multiplexed Bluetooth GPIO Signals 12.6 I/O States 13. DC Characteristics 13.1 Absolute Maximum Ratings 13.2 Environmental Ratings 13.3 Electrostatic Discharge Specifications 13.4 Recommended Operating Conditions and DC Characteristics 14. Bluetooth RF Specifications 15. WLAN RF Specifications 15.1 Introduction 15.2 2.4 GHz Band General RF Specifications 15.3 WLAN 2.4 GHz Receiver Performance Specifications 15.4 WLAN 2.4 GHz Transmitter Performance Specifications 15.5 WLAN 5 GHz Receiver Performance Specifications 15.6 WLAN 5 GHz Transmitter Performance Specifications 15.7 General Spurious Emissions Specifications 15.7.1 Transmitter Spurious Emissions Specifications 15.7.2 Receiver Spurious Emissions Specifications 16. Internal Regulator Electrical Specifications 16.1 Core Buck Switching Regulator 16.2 3.3V LDO (LDO3P3) 16.3 2.5V LDO (BTLDO2P5) 16.4 CLDO 16.5 LNLDO 16.6 PCIe LDO 17. System Power Consumption 17.1 WLAN Current Consumption 17.1.1 2.4 GHz Mode 17.1.2 5 GHz Mode 17.2 Bluetooth Current Consumption 18. Interface Timing and AC Characteristics 18.1 SDIO Timing 18.1.1 SDIO Default Mode Timing 18.2 SDIO High-Speed Mode Timing 18.2.1 SDIO Bus Timing Specifications in SDR Modes 18.2.2 SDIO Bus Timing Specifications in DDR50 Mode 18.3 PCI Express Interface Parameters 18.4 JTAG Timing 18.5 SWD Timing 19. Power-Up Sequence and Timing 19.1 Sequencing of Reset and Regulator Control Signals 19.1.1 Description of Control Signals 19.1.2 Control Signal Timing Diagrams 20. Package Information 20.1 Package Thermal Characteristics 20.2 Junction Temperature Estimation and PSIJT Versus THETAJC 20.3 Environmental Characteristics 21. Mechanical Information 22. Ordering Information 23. Additional Information 23.1 Acronyms and Abbreviations 23.2 References 23.3 IoT Resources Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
Single-Chip 5G WiFi IEEE 802.11n/ac MAC/ Baseband/ Radio with Integrated Bluetooth 5.0 The Cypress CYW43455 single-chip device provides the highest level of integration for Internet of Things applications and handheld wireless system with integrated single-stream IEEE 802.11ac MAC/baseband/radio and, Bluetooth 5.0. In IEEE 802.11ac mode, the WLAN operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz channels for data rates of up to 433.3 Mbps. All rates specified in the IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz and 5 GHz transmit amplifiers and receive low-noise amplifiers. Optional external PAs and LNAs are also supported. The WLAN section supports the following host interface options: an SDIO v3.0 interface that can operate in 4b or 1b mode, a high-speed 4-wire UART, and a PCIe1Gen1 (3.0 compliant) interface. The Bluetooth section supports a high-speed 4-wire UART interface. Using advanced design techniques and process technology to reduce active and idle power, the CYW43455 is designed to address the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which simplifies the system power topology and allows for direct operation from a mobile platform battery while maximizing battery life. The CYW43455 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external radios (such as LTE cellular and GPS) is provided via an external interface. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number
BCM43455 CYW43455 BCM43455XKUBG CYW43455XKUBG BCM43455HKUBG CYW43455HKUBG BCM4329 CYW4329 BCM4330 CYW4330
Features IEEE 802.11x Key Features
■ IEEE 802.11ac compliant. ■ Support for optional front-end modules (FEM) with external PAs and LNAs. ■ Support for TurboQAM® (MCS0–MCS8 86 Mbps and MCS0– MCS9 96 Mbps) HT20, 20 MHz channel bandwidth. ■ Supports optional integrated T/R switch for 2.4 GHz band. ■ Single-stream spatial multiplexing up to 433.3 Mbps data rate. ■ Supports RF front-end architecture with a single dual-band antenna shared between Bluetooth and WLAN for lowest ■ Supports 20, 40, and 80 MHz channels with optional SGI (256 QAM modulation). system cost. ■ Shared Bluetooth and WLAN receive signal path eliminates the ■ Full IEEE 802.11a/b/g/n legacy compatibility with enhanced need for an external power splitter while maintaining excellent performance. sensitivity for both Bluetooth and WLAN. ■ Supports explicit IEEE 802.11ac transmit beamforming. ■ Internal fractional-n PLL allows support for a wide range of ■ TX and RX low-density parity check (LDPC) support for reference clock frequencies. improved range and power efficiency. ■ Supports IEEE 802.15.2 external coexistence interface to ■ On-chip power amplifiers and low-noise amplifiers for both optimize bandwidth utilization with other co-located wireless bands. technologies such as LTE or GPS. 1. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface.
Cypress Semiconductor Corporation
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-15051 Rev. *O Revised March 22, 2019 Document Outline 1. CYW43455 Overview 1.1 Overview 1.2 Standards Compliance 2. Power Supplies and Power Management 2.1 Power Supply Topology 2.2 CYW43455 PMU Features 2.3 WLAN Power Management 2.4 PMU Sequencing Each resource is in one of four states: 2.5 Power-Off Shutdown 2.6 Power-Up/Power-Down/Reset Circuits 3. Frequency References 3.1 Crystal Interface and Clock Generation 3.2 External Frequency Reference 3.3 Frequency Selection 3.4 External 32.768 kHz Low-Power Oscillator 4. Bluetooth Subsystem Overview 4.1 Features 4.2 Bluetooth Radio 4.2.1 Transmit 4.2.2 Digital Modulator 4.2.3 Digital Demodulator and Bit Synchronizer 4.2.4 Power Amplifier 4.2.5 Receiver 4.2.6 Digital Demodulator and Bit Synchronizer 4.2.7 Receiver Signal Strength Indicator 4.2.8 Local Oscillator Generation 4.2.9 Calibration 5. Bluetooth Baseband Core 5.1 Bluetooth 4.0 Features 5.2 Bluetooth 4.2 Features 5.3 Bluetooth Low Energy 5.4 Bluetooth 5.0 5.5 Link Control Layer 5.6 Test Mode Support 5.7 Bluetooth Power Management Unit 5.7.1 RF Power Management 5.7.2 Host Controller Power Management 5.7.3 BBC Power Management 5.8 Adaptive Frequency Hopping 5.9 Advanced Bluetooth/WLAN Coexistence 5.10 Fast Connection (Interlaced Page and Inquiry Scans) 6. Microprocessor and Memory Unit for Bluetooth 6.1 RAM, ROM, and Patch Memory 6.2 Reset 7. Bluetooth Peripheral Transport Unit 7.1 SPI Interface 7.2 SPI/UART Transport Detection 7.3 PCM Interface 7.3.1 Slot Mapping 7.3.2 Frame Synchronization 7.3.3 Data Formatting 7.3.4 Wideband Speech Support 7.3.5 Multiplexed Bluetooth Over PCM 7.3.6 Burst PCM Mode 7.3.7 PCM Interface Timing 7.4 UART Interface 7.5 I2S Interface 7.5.1 I2S Timing 8. WLAN Global Functions 8.1 WLAN CPU and Memory Subsystem 8.2 One-Time Programmable Memory 8.3 GPIO Interface 8.4 External Coexistence Interface 8.5 UART Interface 8.6 JTAG/SWD Interface 9. WLAN Host Interfaces 9.1 SDIO v3.0 9.2 SDIO Pins 9.3 PCI Express Interface 9.4 Transaction Layer Interface 9.4.1 Data Link Layer 9.4.2 Physical Layer 9.4.3 Logical Subblock 9.4.4 Scrambler/Descrambler 9.4.5 8B/10B Encoder/Decoder 9.4.6 Elastic FIFO 9.4.7 Electrical Subblock 9.4.8 Configuration Space 10. Wireless LAN MAC and PHY 10.1 IEEE 802.11ac MAC 10.1.1 PSM 10.1.2 WEP 10.1.3 TXE 10.1.4 RXE 10.1.5 IFS 10.1.6 TSF 10.1.7 NAV 10.1.8 MAC-PHY Interface 10.2 IEEE 802.11ac PHY 11. WLAN Radio Subsystem 11.1 Receiver Path 11.2 Transmit Path 11.3 Calibration 12. Ball Map and Pin Descriptions 12.1 Ball Map 12.2 Pin List by Pin Number 12.3 Pin List by Pin Name 12.4 Pin Descriptions 12.5 WLAN GPIO Signals and Strapping Options 12.5.1 Multiplexed Bluetooth GPIO Signals 12.6 I/O States 13. DC Characteristics 13.1 Absolute Maximum Ratings 13.2 Environmental Ratings 13.3 Electrostatic Discharge Specifications 13.4 Recommended Operating Conditions and DC Characteristics 14. Bluetooth RF Specifications 15. WLAN RF Specifications 15.1 Introduction 15.2 2.4 GHz Band General RF Specifications 15.3 WLAN 2.4 GHz Receiver Performance Specifications 15.4 WLAN 2.4 GHz Transmitter Performance Specifications 15.5 WLAN 5 GHz Receiver Performance Specifications 15.6 WLAN 5 GHz Transmitter Performance Specifications 15.7 General Spurious Emissions Specifications 15.7.1 Transmitter Spurious Emissions Specifications 15.7.2 Receiver Spurious Emissions Specifications 16. Internal Regulator Electrical Specifications 16.1 Core Buck Switching Regulator 16.2 3.3V LDO (LDO3P3) 16.3 2.5V LDO (BTLDO2P5) 16.4 CLDO 16.5 LNLDO 16.6 PCIe LDO 17. System Power Consumption 17.1 WLAN Current Consumption 17.1.1 2.4 GHz Mode 17.1.2 5 GHz Mode 17.2 Bluetooth Current Consumption 18. Interface Timing and AC Characteristics 18.1 SDIO Timing 18.1.1 SDIO Default Mode Timing 18.2 SDIO High-Speed Mode Timing 18.2.1 SDIO Bus Timing Specifications in SDR Modes 18.2.2 SDIO Bus Timing Specifications in DDR50 Mode 18.3 PCI Express Interface Parameters 18.4 JTAG Timing 18.5 SWD Timing 19. Power-Up Sequence and Timing 19.1 Sequencing of Reset and Regulator Control Signals 19.1.1 Description of Control Signals 19.1.2 Control Signal Timing Diagrams 20. Package Information 20.1 Package Thermal Characteristics 20.2 Junction Temperature Estimation and PSIJT Versus THETAJC 20.3 Environmental Characteristics 21. Mechanical Information 22. Ordering Information 23. Additional Information 23.1 Acronyms and Abbreviations 23.2 References 23.3 IoT Resources Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
