Datasheet ADIN1100 (Analog Devices)

Robust, Industrial, Low Power 10BASE-T1L Ethernet PHY Preliminary Technical Data ADIN1100 FEATURES GENERAL DESCRIPTION 10BASE-T1L IEEE® Std 802.3cg-2019TM compliant
The ADIN1100 is a low power single port 10BASE-T1L
Supports 1.0 V pk-pk & 2.4 V pk-pk transmit levels
transceiver designed for industrial Ethernet applications and is
Auto-Negotiation capability
compliant with the IEEE 802.3cg Ethernet standard for long
Supports intrinsic safety applications
reach 10 Mb/s Single Pair Ethernet. It integrates an Ethernet
MII, RMII & RGMII MAC interfaces
PHY core with all the associated analog circuitry, input and
MDIO Management Interface
output clock buffering, the management interface control
Unmanaged configuration using pin strapping including:
register and subsystem registers, as well as the MAC interface
Master/Slave selection
and control logic to manage the reset and clock control and pin
Transmit amplitude
configuration.
PHY address
The PHY core supports the 1.0 V pk-pk operating mode and
25 MHz crystal oscillator/25 MHz external clock input
the 2.4 V pk-pk operating mode defined in the standard and
(50 MHz external clock for RMII)
can operate from a single power supply rail of 1.8V or 3.3V,
Single supply 1.8 V/3.3 V operation (mode dependent)
with the lower voltage option supporting the 1.0 V pk-pk
EMC test standards
transmit voltage level.
IEC 61000-4-4 electrical fast transient (EFT) (±4 kV) IEC 61000-4-2 ESD (±8 kV contact discharge)
The 1.0 V pk-pk operating mode, external termination resistors
IEC 61000-4-2 ESD (±15 kV air discharge)
and independent Rx/Tx pins make the ADIN1100 suited to
IEC 61000-4-6 conducted immunity (10 V)
intrinsic safety applications.
EN55032 radiated emissions (Class A)
The ADIN1100 has an integrated voltage supply monitoring
Cable Reach
circuit and power on reset circuitry to improve system level
1700 meters+ with 1.0 V pk-pk
robustness.
1700 meters+ with 2.4 V pk-pk Low power consumption
The MDIO interface is a two-wire serial interface for
Single supply 1 V pk-pk – 45 mW typ
communication between a host processor or MAC and the
Dual supply 1 V pk-pk – 39 mW typ
ADIN1100, thereby allowing access to control and status
Single supply 2.4 V pk-pk – 109 mW typ
information in the PHY core management registers. This
Dual supply 2.4 V pk-pk – 81 mW typ
interface is compatible with both the IEEE 802.3 Standard
Triple supply 2.4 V pk-pk – 75 mW typ
Clause 22 and Clause 45 management frame structures.
3.3 V/2.5 V/1.8 V MAC interface VDDIO supply
The ADIN1100 is available in a 6 mm x 6 mm 40-ld package.
Integrated power supply monitoring and POR Start of packet detection for IEEE 1588 time stamp support Table 1. Related Products. Diagnostics Product No. Description Frame Generator and Checker
ADIN1110 Robust, Industrial, Low Power
Multiple Loopback Modes
10BASE-T1L Ethernet MAC-
IEEE Test Mode Support
PHY
Cable Diagnostics Link/Activity LED Small package 40-lead (6 mm x 6 mm) LFCSP Industrial temperature range -40°C to 105°C APPLICATIONS Process Control Factory Automation Building Automation Rev.
PrG
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Document Outline Features Applications General Description Functional Block Diagram Specifications Timing Characteristics Power-Up Timing Management Interface Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Theory of Operation Power Supply Domains MAC Interface MII Interface Mode RMII Interface Mode RGMII Interface Mode Auto-Negotiation Transmit Amplitude Resolution Master/Slave Resolution Management Interface Interrupt (INT_N) MDI Interface Reset Operation Power-On Reset Hardware Reset Software Reset PHY Subsystem Reset MAC Interface Reset Status LEDs LED Function Link Status Pin Powerdown Modes Hardware Powerdown Mode Software Powerdown Mode Hardware Configuration Pins Hardware Configuration Pin Functions PHY Address Configuration Software Powerdown after Reset Master/Slave Preference Transmit Amplitude MAC Interface Selection Media Convertor Bringing Up 10BASE-T1L Links Unmanaged PHY Operation Managed PHY Operation Power-up and Reset Complete Configuring the Part for Linking Advertisement of Transmit Level Operating Mode Advertisement of Master/Slave Successful Completion of Auto-Negotiation Link Status On-Chip Diagnostics Loopback Modes PMA Loopback PCS Loopback MAC Interface Loopback MAC Interface Remote Loopback External MII/RMII Loopback Frame Generator and Checker Frame Generator and Checker used with Remote Loopback with Two PHYs Test Modes Accessing the test modes Applications Information System Level Power Management Transmit Level = 1.0 V pk-pk Transmit Level = 2.4 V pk-pk Component Recommendations Crystal External Clock Input Register Summary Clause 22 Clause 45 Recommended Register Operation Latch Low Registers IEEE Duplicated Registers Read Modify Write Operation Clause 22 Register Details MII Control Register MII Status Register PHY Identifier 1 Register PHY Identifier 2 Register MMD Access Control Register MMD Access Register Clause 45 Register Details PMA/PMD Control 1 Register PMA/PMD Status 1 Register PMA/PMD MMD Devices in Package 1 Register PMA/PMD MMD Devices in Package 2 Register PMA/PMD Control 2 Register PMA/PMD Status 2 Register PMA/PMD Transmit Disable Register PMA/PMD Extended Abilities Register BASE-T1 PMA/PMD Extended Ability Register BASE-T1 PMA/PMD Control Register 10BASE-T1L PMA Control Register 10BASE-T1L PMA Status Register 10BASE-T1L Test Mode Control Register Frequency Offset Saturation Threshold for CR Stability Check Register Slave IIR Filter Change Echo Acquisition Clock Recovery Proportional Gain Register 10BASE-T1L PMA Link Status Register MSE Value Register PCS Control 1 Register PCS Status 1 Register PCS MMD Devices in Package 1 Register PCS MMD Devices in Package 2 Register PCS Status 2 Register 10BASE-T1L PCS Control Register 10BASE-T1L PCS Status Register AUTO-_NEGOTIATION MMD Devices in Package 1 Register AUTO-_NEGOTIATION MMD Devices in Package 2 Register BASE-T1 Autonegotiation Control Register BASE-T1 Autonegotiation Status Register BASE-T1 Autonegotiation Advertisement [15:0] Register BASE-T1 Autonegotiation Advertisement [31:16] Register BASE-T1 Autonegotiation Advertisement [47:32] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [15:0] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [31:16] Register BASE-T1 Autonegotiation Link Partner Base Page Ability [47:32] Register BASE-T1 Autonegotiation Next Page Transmit [15:0] Register BASE-T1 Autonegotiation Next Page Transmit [31:16] Register BASE-T1 Autonegotiation Next Page Transmit [47:32] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [15:0] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [31:16] Register BASE-T1 Autonegotiation Link Partner Next Page Ability [47:32] Register 10BASE-T1 Autonegotiation Control Register 10BASE-T1 Autonegotiation Status Register Extra Autonegotiation Status Register PHY Instantaneous Status Register Vendor Specific MMD 1 Device Identifier High Register Vendor Specific MMD 1 Device Identifier Low Register Vendor Specific 1 MMD Devices in Package Register Vendor Specific 1 MMD Devices in Package Register Vendor Specific MMD 1 Status Register System Interrupt Status Register System Interrupt Mask Register Software Reset Register Software Power-down Control Register PHY Subsystem Reset Register PHY MAC Interface Reset Register System Status Register CRSM Power Management Control Register MAC Interface Configuration Register CRSM Diagnostics Clock Control Register Package Configuration Values Register MDIO Control Register Pinmux Configuration 1 Register Pinmux Configuration 2 Register LED 0 ON/_OFF Blink Time Register LED 1 ON/_OFF Blink Time Register LED Control Register LED Polarity Register Vendor Specific MMD 2 Device Identifier High Register Vendor Specific MMD 2 Device Identifier Low Register Vendor Specific 2 MMD Devices in Package Register Vendor Specific 2 MMD Devices in Package Register Vendor Specific MMD 2 Status Register PHY Subsystem Interrupt Status Register PHY Subsystem Interrupt Mask Register Frame Checker Enable Register Frame Checker Interrupt Enable Register Frame Checker Transmit Select Register Receive Error Count Register Frame Checker Count High Register Frame Checker Count Low Register Frame Checker Length Error Count Register Frame Checker Alignment Error Count Register Frame Checker Symbol Error Count Register Frame Checker Oversized Frame Count Register Frame Checker Undersized Frame Count Register Frame Checker Odd Nibble Frame Count Register Frame Checker Odd Preamble Packet Count Register Frame Checker False Carrier Count Register Frame Generator Enable Register Frame Generator CONTROL/_RESTART Register Frame Generator Continuous Mode Enable Register Frame Generator Interrupt Enable Register Frame Generator Frame Length Register Frame Generator Number of Frames High Register Frame Generator Number of Frames Low Register Frame Generator Done Register RMII Configuration Register MAC Interface Loopbacks Configuration Register MAC Start Of Packet (SOP) Generation Control Register PCB Layout Recommendations PHY Package Layout Component Placement Crystal Placement and Routing Outline Dimensions