Datasheet PMG1-S2 (Infineon) - 9

PMG1-S2 Datasheet
Functional Overview
CPU and Memory Subsystem USB-PD Subsystem (USBPD SS) CPU The USB-PD subsystem contains all of the blocks related to USB
Type-C and Power Delivery. The subsystem consists of the
following: The Cortex-M0 CPU in PMG1-S2 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. The Cypress
implementation includes a hardware multiplier that provides a
32-bit result in one cycle. It includes a nested vectored interrupt
controller (NVIC) block with 32 interrupt inputs and also includes
a Wakeup Interrupt Controller (WIC). The WIC can wake the
processor up from the Deep Sleep mode, allowing power to be
switched off to the main processor when the chip is in the Deep
Sleep mode. The Cortex-M0 CPU provides a Non-Maskable
Interrupt (NMI) input, which is made available to the user when
it is not in use for system functions requested by the user.
The CPU also includes a serial wire debug (SWD) interface,
which is a two-wire form of JTAG. The debug configuration used
for PMG1-S2 has four break-point (address) comparators and
two watchpoint (data) comparators.
Flash
The PMG1-S2 device has a flash module with two banks of 64
KB flash, a flash accelerator, tightly coupled to the CPU to
improve average access times from the flash block. The flash
block is designed to deliver 1 wait-state (WS) access time at
48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average.
SROM
A supervisory ROM that contains boot and configuration routines
is provided. Crypto Block
PMG1-S2 integrates a crypto block for hardware assisted
authentication of firmware images. It also supports field
upgradeability of firmware in a trusted ecosystem. The PMG1-S2
Crypto block provides cryptography functionality. It includes
hardware acceleration blocks for Advanced Encryption Standard
(AES) block cipher, Secure Hash Algorithm (SHA-1 and SHA-2),
Cyclic Redundancy Check (CRC) and pseudo random number
generation. Integrated Billboard Device
PMG1-S2 integrates a complete full speed USB 2.0 device
controller capable of functioning as a Billboard class device. The
USB 2.0 device controller can also support other device classes. Document Number: 002-31598 Rev. *B ■ Biphase Marked Coding (BMC) PHY: USB-PD Transceiver with
Fast Role Swap (FRS) transmit and detect ■ VCONN power FETs for the CC lines ■ Analog Crossbar to switch between the SBU1/SBU2 and
AUX_P/AUX_N pins ■ Programmable pull-up and pull-down termination on the
AUX_P/AUX_N pins ■ Hot Plug Detect (HPD) processor ■ VBUS_C regulator (20V LDO) ■ Power switch between VSYS supply and VBUS_C regulator
output ■ VBUS_C overvoltage (OV) and undervoltage (UV) detectors ■ Current sense amplifier (CSA) for overcurrent detection ■ Gate Drivers for VBUS_P and VBUS_C external Power FETs ■ VBUS_C discharge switch ■ Charger Detection/Emulation for USB BC1.2 and other
proprietary protocols ■ Two instances of 8-bit SAR ADCs ■ 8-kV IEC ESD Protection on the following pins: VBUS_C, CC1,
CC2, SBU1, SBU2, USBDP, USBDM The PMG1-S2 USB-PD subsystem interfaces to the pins of a
USB Type-C connector. It includes a USB Type-C baseband
transceiver and physical-layer logic. This transceiver performs
the BMC and the 4b/5b encoding and decoding functions as well
as integrating the 1.2-V analog front end (AFE). This subsystem
integrates the required terminations to identify the role of the
PMG1-S2 device, including RP and RD for UFP/DFP roles. It also
integrates power FETs for supplying VCONN power to the
CC1/CC2 pins from the VCONN_Source pin. The analog
crossbar enables connecting either of the SBU1/SBU2 pins to
either of the AUX_P/AUX_N pins to support DisplayPort
sideband signaling. The integrated HPD processor can be used
to control or monitor the HPD signal of a DisplayPort source or
sink. Page 8 of 33