IRL540 www.vishay.com Vishay Siliconix L V V DS DS Vary tp to obtain t required I p AS VDD R D.U.T. G + V - DD V I DS AS 5 V t 0.01 p Ω IAS Fig. 12a - Unclamped Inductive Test CircuitFig. 12b - Unclamped Inductive WaveformsFig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. Q 50 kΩ G VGS 12 V 0.2 µF 0.3 µF Q Q GS GD + V D.U.T. DS - VG VGS 3 mA Charge I I G D Current sampling resistors Fig. 13a - Basic Gate Charge WaveformFig. 13b - Gate Charge Test Circuit S21-1046-Rev. C, 25-Oct-2021 6 Document Number: 91300 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000