Datasheet RAA227063 (Renesas) - 9

RAA227063 Datasheet 2. Pin Information 2.1 Pin Assignments L1 E S_S N L2 /S E 1 FO _S M SEL E NS C PH /B /S E C B A O D /B C O O O XVC LD N EF C C C S U VC C CS CS A FB SG VR SN SPC GL GH 48 47 46 45 44 43 42 41 40 39 38 37 LIC 1 36 SHC HIC 2 35 SNB/BEPHSEL2 LIB 3 34 SPB HIB 4 33 GLB LIA 5 32 SHB HIA 6 31 GHB
Thermal Pad
EN 7 30 SNA nFAULT 8 29 SPA IDRV/SDI 9 28 GLA MODE/SDO 10 27 SHA CSGAIN/SCLK 11 26 GHA VDSTH/nSCS 12 25 VCP 13 14 15 16 17 18 19 20 21 22 23 24 P 1 2 D V L H E N EN M FB VM N R SW SW CP CP DG /B CO PG VD RI MMO B V O C T/IFSEL D
Top View
2.2 Pin Descriptions Pin # Pin Name Description
1 LIC Phase C low-side driver control input. 2 HIC Phase C high-side driver control input. 3 LIB Phase B low-side driver control input. 4 HIB Phase B high-side driver control input. 5 LIA Phase A low-side driver control input. 6 HIA Phase A high-side driver control input. R16DS0045EU0101 Rev.1.01 Page 9 Nov 29, 2021 Document Outline Applications Features Contents 1. Overview 1.1 Typical Application Circuits 2. Pin Information 2.1 Pin Assignments 2.2 Pin Descriptions 3. Specifications 3.1 Absolute Maximum Ratings 3.2 Thermal Information 3.3 Recommended Operating Conditions 3.4 Electrical Specifications 4. Typical Performance Curves 5. Functional Description 5.1 Modes of Operation and Power-On Sequence 5.1.1 Definitions of State of Different Modes 5.1.2 Mode Transition 5.1.3 Modes of Operation 5.1.3.1 Gate Driver Control Modes 5.1.3.2 3-phase HI/LI Mode 5.1.3.3 3-phase PWM Mode 5.1.4 Gate Driver Structure and Feature 5.1.4.1 Driver Structure 5.1.4.2 Adjustable Slew-Rate 5.1.4.3 Driver Robustness Enhancement 5.1.4.4 Gate Drive Diagram 5.1.4.5 Gate Drive Scheme in 3-phase HI/LI Mode 5.1.5 Power Architecture 5.1.5.1 Power Architecture Overview 5.1.5.2 Low-Side Driver Supply (VDRV) 5.1.5.3 Charge Pump 5.1.5.4 VCC Supply 5.1.5.5 MCU AUXVCC Supply 5.1.6 Power-On Sequence 5.2 Fault Management 5.2.1 Fault Conditions Types 5.2.2 nFAULT Indicator 5.3 Current Sensing and BEMF Sensing 5.3.1 Overview 5.3.2 Details on Different Sensing Configurations 5.3.2.1 Configuration 1 5.3.2.2 Configuration 2 5.3.2.3 Configuration 3 5.3.2.4 Configuration 4 5.3.2.5 Configuration 5 5.3.2.6 Configuration 6 5.3.2.7 Configuration 7 5.3.2.8 Configuration 8 5.3.2.9 Configuration 9 5.3.3 Structure of Amplifiers CSA, CSB, and CSC 5.3.4 BEMF Sensing Control Signal Logic 5.3.5 Multiplexer Control Signal Logic 5.3.6 Sample and Hold Timing Logic 5.3.7 Low-Side rDS(ON) Current Sensing Timing Logic 5.4 Hardware Interface for Parameter Setting 5.4.1 Parameter Setting Tables 5.5 Serial Peripheral Interface (SPI) 5.5.1 Communication Protocol 5.5.2 Timing Diagram 6. Register Map 7. Package Outline Drawing 8. Ordering Information 9. Revision History