Datasheet SG1524, SG2524, SG3524 (Microchip) - 4
| Manufacturer | Microchip |
| Description | Regulating Pulse Width Modulator |
| Pages / Page | 9 / 4 — OSCILLATOR. 100k. 50k. 20k. 10k. 0.5. 0.2. .001 .002 .005 .01 .02. .05 … |
| File Format / Size | PDF / 866 Kb |
| Document Language | English |
OSCILLATOR. 100k. 50k. 20k. 10k. 0.5. 0.2. .001 .002 .005 .01 .02. .05 0.1. 500. 50k 100k 200k 500k. Figure 2 · Output Stage Deadtime vs. CT
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Text Version of Document
Application Notes
OSCILLATOR
The oscillator in the SG1524 uses an external resistor RT to Note that for buck regulator topologies, the two outputs can be establish a constant charging current into an external capacitor wire-ORed for an effective 0-90% duty cycle range. With this CT. While this uses more current than a series-connected RC, it connection, the output frequency is the same as the oscillator provides a linear ramp voltage at CT which is used as a time- frequency. For push-pull applications, the outputs are used dependent reference for the PWM comparator. The charging separately; the flip-flop limits the duty cycle range at each output current is equal to 3.6V/RT, and should be restricted to between to 0-45%, and the effective switching frequency at the trans- 30µA and 2mA. The equivalent range for RT is 100k to 1.8k. former is 1/2 the oscillator frequency. The range of values for CT also has limits, as the discharge time If it is desired to synchronize the SG1524 to an external clock, a of CT determines the pulse width of the oscillator output pulse. positive pulse may be applied to the clock pin. The oscillator The pulse is used (among other things) as a blanking pulse to should be programmed with RT and CT values that cause it to both outputs to insure that there is no possibility of having both free-run at 90% of the external sync frequency. A sync pulse outputs on simultaneously during transitions. This output with a maximum logic 0 of +0.3 volts and a minimum logic 1 of deadtime relationship is shown in Figure 2. A pulse width below +2.4 volts applied to Pin 3 will lock the oscillator to the external 0.35 microseconds may cause failure of the internal flip-flop to source. The minimum sync pulsewidth should be 200 toggle. This restricts the minimum value of CT to 1000pF. (Note: nanoseconds, and the maximum is determined by the required Although the oscillator output is a convenient oscilloscope sync deadtime. The clock pin should never be driven more negative input, the probe capacitance will increase the pulse width and than -0.3 volts, nor more positive than +5.0 volts. The decrease the oscillator frequency slightly.) Obviously, the upper nominal resistance to ground is 3.2k at the clock pin, ±25% limit to the pulse width is determined by the modulation range over temperature. required in the power supply at the chosen switching frequency. Practical values of CT fall between 1000pF and 0.1µF, although If two or more SG1524's must be synchronized together, program successful 120 Hz oscillators have been implemented with one master unit with RT and CT for the desired frequency. values up to 5µF and a series surge limit resistor of 100 ohms. Leave the RT pins on the slaves open, connect the CT pins to the CT of the master, and connect the clock pins to the clock pin The oscillator frequency is approximately 1/RT•CT; where R is in of the master. Since CT is a high-impedance node, this sync ohms, C is in microfarads, and the frequency is in Megahertz. technique works best when all devices are close together. For greater accuracy, the chart in Figure 3 may be used for a wide range of operating frequencies.
20 100k 10 50k 5 20k 2 10k 1 5k 0.5 2k 1k 0.2 .001 .002 .005 .01 .02 .05 0.1 500 1k 2k 5k 10k 20k 50k 100k 200k 500k Figure 2 · Output Stage Deadtime vs. CT Figure 3 · Oscillator Frequency vs. RT and CT
4 Document Outline Regulating Pulse Width Modulator Description Features High Reliability Features Block Diagram Absolute Maximum Ratings Thermal Data Recommended Operating Conditions Electrical Characteristics Electrical Characteristics (Continued) Application Notes Application Notes (Continued) Connection Diagrams and Ordering Information Package Outline Dimensions Package Outline Dimensions (continued)
OSCILLATOR
The oscillator in the SG1524 uses an external resistor RT to Note that for buck regulator topologies, the two outputs can be establish a constant charging current into an external capacitor wire-ORed for an effective 0-90% duty cycle range. With this CT. While this uses more current than a series-connected RC, it connection, the output frequency is the same as the oscillator provides a linear ramp voltage at CT which is used as a time- frequency. For push-pull applications, the outputs are used dependent reference for the PWM comparator. The charging separately; the flip-flop limits the duty cycle range at each output current is equal to 3.6V/RT, and should be restricted to between to 0-45%, and the effective switching frequency at the trans- 30µA and 2mA. The equivalent range for RT is 100k to 1.8k. former is 1/2 the oscillator frequency. The range of values for CT also has limits, as the discharge time If it is desired to synchronize the SG1524 to an external clock, a of CT determines the pulse width of the oscillator output pulse. positive pulse may be applied to the clock pin. The oscillator The pulse is used (among other things) as a blanking pulse to should be programmed with RT and CT values that cause it to both outputs to insure that there is no possibility of having both free-run at 90% of the external sync frequency. A sync pulse outputs on simultaneously during transitions. This output with a maximum logic 0 of +0.3 volts and a minimum logic 1 of deadtime relationship is shown in Figure 2. A pulse width below +2.4 volts applied to Pin 3 will lock the oscillator to the external 0.35 microseconds may cause failure of the internal flip-flop to source. The minimum sync pulsewidth should be 200 toggle. This restricts the minimum value of CT to 1000pF. (Note: nanoseconds, and the maximum is determined by the required Although the oscillator output is a convenient oscilloscope sync deadtime. The clock pin should never be driven more negative input, the probe capacitance will increase the pulse width and than -0.3 volts, nor more positive than +5.0 volts. The decrease the oscillator frequency slightly.) Obviously, the upper nominal resistance to ground is 3.2k at the clock pin, ±25% limit to the pulse width is determined by the modulation range over temperature. required in the power supply at the chosen switching frequency. Practical values of CT fall between 1000pF and 0.1µF, although If two or more SG1524's must be synchronized together, program successful 120 Hz oscillators have been implemented with one master unit with RT and CT for the desired frequency. values up to 5µF and a series surge limit resistor of 100 ohms. Leave the RT pins on the slaves open, connect the CT pins to the CT of the master, and connect the clock pins to the clock pin The oscillator frequency is approximately 1/RT•CT; where R is in of the master. Since CT is a high-impedance node, this sync ohms, C is in microfarads, and the frequency is in Megahertz. technique works best when all devices are close together. For greater accuracy, the chart in Figure 3 may be used for a wide range of operating frequencies.
20 100k 10 50k 5 20k 2 10k 1 5k 0.5 2k 1k 0.2 .001 .002 .005 .01 .02 .05 0.1 500 1k 2k 5k 10k 20k 50k 100k 200k 500k Figure 2 · Output Stage Deadtime vs. CT Figure 3 · Oscillator Frequency vs. RT and CT
4 Document Outline Regulating Pulse Width Modulator Description Features High Reliability Features Block Diagram Absolute Maximum Ratings Thermal Data Recommended Operating Conditions Electrical Characteristics Electrical Characteristics (Continued) Application Notes Application Notes (Continued) Connection Diagrams and Ordering Information Package Outline Dimensions Package Outline Dimensions (continued)
