Datasheet AEM00940 (E-peas) - 7
| Manufacturer | E-peas |
| Description | Highly efficient, regulated dual-output, ambient energy manager for Source Voltage Level Configuration with optional primary battery |
| Pages / Page | 29 / 7 — DATASHEET. AEM00940. 2. Absolute Maximum Ratings. 3. Thermal Resistance |
| File Format / Size | PDF / 2.2 Mb |
| Document Language | English |
DATASHEET. AEM00940. 2. Absolute Maximum Ratings. 3. Thermal Resistance
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DATASHEET AEM00940
NAME PIN NUMBER FUNCTION Control pins ENHV 12 Enabling pin for the high-voltage LDO. See table 8 ENLV 18 Enabling pin for the low-voltage LDO. Status pins STATUS[1] 20 Logic output. Asserted if the battery voltage fal s below VOVDIS or if the AEM is taking energy from the primary battery. STATUS[0] 21 Logic output. Asserted when the LDOs can be enabled. Other pins GND Exposed pad Ground connection, should be solidly tied to the PCB ground plane Table 2: Pins description (Part 2)
2. Absolute Maximum Ratings 3. Thermal Resistance
Parameter Rating Package θJA θJC Unit VSRC 5.5 V TBD 38.3 2.183 °C/W Operating junction temperature - 40 °C to + 125 °C Table 4: Thermal data Storage temperature - 65 °C to + 150 °C Table 3: Absolute maximum ratings ESD CAUTION ESD (ELECTROSTATIC DISCHARGE) SENSITIVE DEVICE These devices have limited built-in ESD protection and damage may thus occur on devices subjected to high-energy ESD. Therefore, proper EESD precautions should be taken to avoid performance degradation or loss of functionality Human-body model according to Jedec JS001-2017 ± 500 V VESD Charge device model according to Jedec JS002-2014 ± 1000 V Table 5: ESD caution DS D _A _ E A M0 M 094 9 0_Rev e 1.0. 0 0 Copyr y ight h © 2022 2 e-pe p as a SA S Confidential 7 Document Outline 1. Introduction 2. Absolute Maximum Ratings 3. Thermal Resistance 4. Typical Electrical Characteristics at 25 °C 5. Recommended Operation Conditions 6. Functional Block Diagram 7. Theory of Operation 7.1. Deep sleep & Wake up modes 7.1.1. Supercapacitor as a storage element. 7.1.2. Battery as a storage element. 7.2. Normal mode 7.2.1. Boost 7.2.2. Buck 7.2.3. LDO outputs 7.3. Overcharge mode 7.4. Primary mode 7.5. Shutdown mode 7.6. Balun for dual-cell supercapacitor 8. System configuration 8.1. Battery and LDOs configuration 8.1.1. Custom mode 8.2. Source voltage configuration 8.3. Primary battery configuration 8.4. No-battery configuration 8.5. Storage element information 8.6. External inductors information 8.7. External capacitors information 9. Typical Application Circuits 9.1. Example circuit 1 9.2. Example circuit 2 10. Performance Data 10.1. BOOST conversion efficiency for LBOOST = 10 µH 10.2. BOOST conversion efficiency for LBOOST = 22 µH 10.3. Quiescent current 10.4. High-voltage LDO regulation 10.5. Low-voltage LDO regulation 10.6. High-voltage LDO efficiency 10.7. Low-voltage LDO efficiency 11. Schematic 12. Layout Package Information 13.1. Plastic Quad Flatpack No-lead (QFN 28-pin 5x5mm) 13.2. Board Layout 14. Revision History
DATASHEET AEM00940
NAME PIN NUMBER FUNCTION Control pins ENHV 12 Enabling pin for the high-voltage LDO. See table 8 ENLV 18 Enabling pin for the low-voltage LDO. Status pins STATUS[1] 20 Logic output. Asserted if the battery voltage fal s below VOVDIS or if the AEM is taking energy from the primary battery. STATUS[0] 21 Logic output. Asserted when the LDOs can be enabled. Other pins GND Exposed pad Ground connection, should be solidly tied to the PCB ground plane Table 2: Pins description (Part 2)
2. Absolute Maximum Ratings 3. Thermal Resistance
Parameter Rating Package θJA θJC Unit VSRC 5.5 V TBD 38.3 2.183 °C/W Operating junction temperature - 40 °C to + 125 °C Table 4: Thermal data Storage temperature - 65 °C to + 150 °C Table 3: Absolute maximum ratings ESD CAUTION ESD (ELECTROSTATIC DISCHARGE) SENSITIVE DEVICE These devices have limited built-in ESD protection and damage may thus occur on devices subjected to high-energy ESD. Therefore, proper EESD precautions should be taken to avoid performance degradation or loss of functionality Human-body model according to Jedec JS001-2017 ± 500 V VESD Charge device model according to Jedec JS002-2014 ± 1000 V Table 5: ESD caution DS D _A _ E A M0 M 094 9 0_Rev e 1.0. 0 0 Copyr y ight h © 2022 2 e-pe p as a SA S Confidential 7 Document Outline 1. Introduction 2. Absolute Maximum Ratings 3. Thermal Resistance 4. Typical Electrical Characteristics at 25 °C 5. Recommended Operation Conditions 6. Functional Block Diagram 7. Theory of Operation 7.1. Deep sleep & Wake up modes 7.1.1. Supercapacitor as a storage element. 7.1.2. Battery as a storage element. 7.2. Normal mode 7.2.1. Boost 7.2.2. Buck 7.2.3. LDO outputs 7.3. Overcharge mode 7.4. Primary mode 7.5. Shutdown mode 7.6. Balun for dual-cell supercapacitor 8. System configuration 8.1. Battery and LDOs configuration 8.1.1. Custom mode 8.2. Source voltage configuration 8.3. Primary battery configuration 8.4. No-battery configuration 8.5. Storage element information 8.6. External inductors information 8.7. External capacitors information 9. Typical Application Circuits 9.1. Example circuit 1 9.2. Example circuit 2 10. Performance Data 10.1. BOOST conversion efficiency for LBOOST = 10 µH 10.2. BOOST conversion efficiency for LBOOST = 22 µH 10.3. Quiescent current 10.4. High-voltage LDO regulation 10.5. Low-voltage LDO regulation 10.6. High-voltage LDO efficiency 10.7. Low-voltage LDO efficiency 11. Schematic 12. Layout Package Information 13.1. Plastic Quad Flatpack No-lead (QFN 28-pin 5x5mm) 13.2. Board Layout 14. Revision History
