Datasheet ADGS1408, ADGS1409 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | SPI Interface, 4 Ω RON, ±15 V/+12 V/±5 V, 1.8 V Logic Control, 8:1/Dual 4:1 Muxes |
| Pages / Page | 34 / 10 — ADGS1408/. ADGS1409. Data Sheet. TIMING CHARACTERISTICS. Table 6. … |
| File Format / Size | PDF / 502 Kb |
| Document Language | English |
ADGS1408/. ADGS1409. Data Sheet. TIMING CHARACTERISTICS. Table 6. Parameter. Limit. Unit. Test Conditions/Comments. Timing Diagrams. SCLK
Model Line for this Datasheet
Text Version of Document
ADGS1408/ ADGS1409 Data Sheet TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.
Table 6. Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTERISTICS t1 20 ns min SCLK or CNV period t2 8 ns min SCLK or CNV high pulse width t3 8 ns min SCLK or CNV low pulse width t4 10 ns min CS falling edge to SCLK or CNV active edge t5 6 ns min Data setup time t6 8 ns min Data hold time t7 10 ns min SCLK or CNV active edge to CS rising edge t8 20 ns max CS falling edge to SDO data available t 1 9 20 ns max SCLK falling edge to SDO data available t10 20 ns max CS rising edge to SDO returns to high impedance t11 20 ns min CS high time between SPI commands t12 8 ns min CS falling edge to SCLK/CNV becomes stable t13 8 ns min CS rising edge to SCLK/CNV becomes stable 1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams t1 SCLK t2 t t 4 t3 7 CS t t 6 5 SDI R/W A6 A5 D2 D1 D0 t t 9 10 SDO 0 0 1 D2 D1 D0
2 -10
t8
791 16 Figure 3. Address Mode Timing Diagram Rev. 0 | Page 10 of 34 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±5 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES CRC Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Detection CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET ROUND ROBIN MODE GENERAL-PURPOSE OUTPUTS (GPOs) APPLICATIONS INFORMATION DIGITAL INPUT BUFFERS POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS POWER SUPPLY SEQUENCING REGISTER SUMMARIES REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER ROUND ROBIN ENABLE REGISTER ROUND ROBIN CHANNEL CONFIGURATION REGISTER CNV EDGE SELECT REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.
Table 6. Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTERISTICS t1 20 ns min SCLK or CNV period t2 8 ns min SCLK or CNV high pulse width t3 8 ns min SCLK or CNV low pulse width t4 10 ns min CS falling edge to SCLK or CNV active edge t5 6 ns min Data setup time t6 8 ns min Data hold time t7 10 ns min SCLK or CNV active edge to CS rising edge t8 20 ns max CS falling edge to SDO data available t 1 9 20 ns max SCLK falling edge to SDO data available t10 20 ns max CS rising edge to SDO returns to high impedance t11 20 ns min CS high time between SPI commands t12 8 ns min CS falling edge to SCLK/CNV becomes stable t13 8 ns min CS rising edge to SCLK/CNV becomes stable 1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams t1 SCLK t2 t t 4 t3 7 CS t t 6 5 SDI R/W A6 A5 D2 D1 D0 t t 9 10 SDO 0 0 1 D2 D1 D0
2 -10
t8
791 16 Figure 3. Address Mode Timing Diagram Rev. 0 | Page 10 of 34 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±5 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES CRC Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Detection CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET ROUND ROBIN MODE GENERAL-PURPOSE OUTPUTS (GPOs) APPLICATIONS INFORMATION DIGITAL INPUT BUFFERS POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS POWER SUPPLY SEQUENCING REGISTER SUMMARIES REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER ROUND ROBIN ENABLE REGISTER ROUND ROBIN CHANNEL CONFIGURATION REGISTER CNV EDGE SELECT REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
