Datasheet ADGS1212 (Analog Devices) - 5

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Data Sheet ADGS1212 12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 2. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range 0 V to VDD V On Resistance, RON 300 Ω typ VS = 0 V to 10 V, IS = −1 mA, see Figure 24 475 567 625 Ω max VDD = 10.8 V, VSS = 0 V On-Resistance Match Between 4.5 Ω typ VS = 0 V to 10 V, IS = −1 mA Channels, ∆RON 12 26 27 Ω max On-Resistance Flatness, RFLAT (ON) 60 Ω typ VS = 3 V/6 V/9 V, IS = −1 mA LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V Source Off Leakage, IS (OFF) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 27 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (OFF) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 27 ±0.1 ±0.6 ±1 nA max Channel On Leakage, ID (ON), IS (ON) ±0.02 nA typ VS = VD = 1 V/10 V, see Figure 23 ±0.1 ±0.6 ±1 nA max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 5 mA 0.2 V max ISINK = 1 mA High or Low Output Current, IOL or IOH 0.001 µA typ Output voltage (VOUT) = ground voltage (VGND) or VL ±0.1 µA max Digital Output Capacitance, COUT 4 pF typ DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Low or High Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VL ±0.1 µA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 On Time, tON 395 ns typ Load resistance (RL) = 300 Ω, load capacitance (CL) = 35 pF 475 485 490 ns max VS = 8 V, see Figure 32 Off Time, tOFF 135 ns typ RL = 300 Ω, CL = 35 pF 170 195 225 ns max VS = 8 V, see Figure 32 Break-Before-Make Time Delay, tD 230 ns typ RL = 300 Ω, CL = 35 pF 170 ns min VS1 = VS2 = 8 V, see Figure 31 Charge Injection, QINJ −0.5 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 33 Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 26 Channel to Channel Crosstalk −110 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 25 −3 dB Bandwidth 900 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 29 Rev. 0 | Page 5 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Four Channels On One Channel On TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET APPLICATIONS INFORMATION BREAK-BEFORE-MAKE SWITCHING POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE