Datasheet ADGS1412 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | SPI Interface, 1.5 Ω RON, ±15 V/+12 V, Quad SPST Switch, Mux Configurable |
| Pages / Page | 27 / 9 — Data Sheet. ADGS1412. CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx. Table 4. … |
| Revision | B |
| File Format / Size | PDF / 534 Kb |
| Document Language | English |
Data Sheet. ADGS1412. CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx. Table 4. Four Channels On Parameter. 25°C. 85°C. 125°C. Unit
Model Line for this Datasheet
Text Version of Document
Data Sheet ADGS1412 CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Table 4. Four Channels On Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx1 VDD = 15 V, VSS = −15 V (θJA = 54°C/W) 297 165 79 mA maximum VDD = 12 V, VSS = 0 V (θJA = 54°C/W) 240 142 74 mA maximum VDD = 5 V, VSS = −5 V (θJA = 54°C/W) 224 135 72 mA maximum 1 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
Table 5. One Channel On Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx1 VDD = 15 V, VSS = −15 V (θJA = 54°C/W) 531 235 87 mA maximum VDD = 12 V, VSS = 0 V (θJA = 54°C/W) 433 210 85 mA maximum VDD = 5 V, VSS = −5 V (θJA = 54°C/W) 404 202 84 mA maximum 1 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.
Table 6. Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTRISTICS t1 20 ns min SCLK period t2 8 ns min SCLK high pulse width t3 8 ns min SCLK low pulse width t4 10 ns min CS falling edge to SCLK active edge t5 6 ns min Data setup time t6 8 ns min Data hold time t7 10 ns min SCLK active edge to CS rising edge t8 20 ns max CS falling edge to SDO data available t 1 9 20 ns max SCLK falling edge to SDO data available t10 20 ns max CS rising edge to SDO returns to high impedance t11 20 ns min CS high time between SPI commands t12 8 ns min CS falling edge to SCLK becomes stable t13 8 ns min CS rising edge to SCLK becomes stable 1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used. Rev. B | Page 9 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±5 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET APPLICATIONS INFORMATION BREAK-BEFORE-MAKE SWITCHING DIGITAL INPUT BUFFERS POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
CONTINUOUS CURRENT, Sx OR Dx1 VDD = 15 V, VSS = −15 V (θJA = 54°C/W) 297 165 79 mA maximum VDD = 12 V, VSS = 0 V (θJA = 54°C/W) 240 142 74 mA maximum VDD = 5 V, VSS = −5 V (θJA = 54°C/W) 224 135 72 mA maximum 1 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
Table 5. One Channel On Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx1 VDD = 15 V, VSS = −15 V (θJA = 54°C/W) 531 235 87 mA maximum VDD = 12 V, VSS = 0 V (θJA = 54°C/W) 433 210 85 mA maximum VDD = 5 V, VSS = −5 V (θJA = 54°C/W) 404 202 84 mA maximum 1 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.
Table 6. Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTRISTICS t1 20 ns min SCLK period t2 8 ns min SCLK high pulse width t3 8 ns min SCLK low pulse width t4 10 ns min CS falling edge to SCLK active edge t5 6 ns min Data setup time t6 8 ns min Data hold time t7 10 ns min SCLK active edge to CS rising edge t8 20 ns max CS falling edge to SDO data available t 1 9 20 ns max SCLK falling edge to SDO data available t10 20 ns max CS rising edge to SDO returns to high impedance t11 20 ns min CS high time between SPI commands t12 8 ns min CS falling edge to SCLK becomes stable t13 8 ns min CS rising edge to SCLK becomes stable 1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used. Rev. B | Page 9 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±5 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET APPLICATIONS INFORMATION BREAK-BEFORE-MAKE SWITCHING DIGITAL INPUT BUFFERS POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
