Datasheet AT89C51 (Microchip) - 5
| Manufacturer | Microchip |
| Description | 8-bit Microcontroller with 4K Bytes Flash |
| Pages / Page | 17 / 5 — AT89C51. Figure 2. Program Memory Lock Bits. Power-down Mode. Lock Bit … |
| File Format / Size | PDF / 145 Kb |
| Document Language | English |
AT89C51. Figure 2. Program Memory Lock Bits. Power-down Mode. Lock Bit Protection Modes. Program Lock Bits. LB1. LB2. LB3
Model Line for this Datasheet
- AT89C51-12AC AT89C51-12AI AT89C51-12JC AT89C51-12JI AT89C51-12PC AT89C51-12PI AT89C51-12QC AT89C51-12QI AT89C51-16AC AT89C51-16AI AT89C51-16JC AT89C51-16JI AT89C51-16PC AT89C51-16PI AT89C51-16QC AT89C51-16QI AT89C51-20AC AT89C51-20AI AT89C51-20JC AT89C51-20JI AT89C51-20PC AT89C51-20PI AT89C51-20QC AT89C51-20QI AT89C51-24AC AT89C51-24AI AT89C51-24JC AT89C51-24JI AT89C51-24PC AT89C51-24PI AT89C51-24QC AT89C51-24QI
Text Version of Document
AT89C51 Figure 2.
External Clock Drive Configuration ters retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unpro- grammed (U) or can be programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is nec-
Power-down Mode
essary that the latched value of EA be in agreement with In the power-down mode, the oscillator is stopped, and the the current logic level at that pin in order for the device to instruction that invokes power-down is the last instruction function properly. executed. The on-chip RAM and Special Function Regis-
Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 Protection Type
1 U U U No program lock features 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled 3 P P U Same as mode 2, also verify is disabled 4 P P P Same as mode 3, also external execution is disabled
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Document Outline Block Diagram Features Description Pin Description VCC GND Port 0 Port 1 Port 2 Port 3 RST ALE/PROG PSEN EA/VPP XTAL1 XTAL2 Oscillator Characteristics Status of External Pins During Idle and Power-down Modes Lock Bit Protection Modes Programming the Flash Programming Interface Flash Programming Modes Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V) Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V) Flash Programming and Verification Characteristics Absolute Maximum Ratings* DC Characteristics AC Characteristics External Program and Data Memory Characteristics External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Float Waveforms(1) Ordering Information
External Clock Drive Configuration ters retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unpro- grammed (U) or can be programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is nec-
Power-down Mode
essary that the latched value of EA be in agreement with In the power-down mode, the oscillator is stopped, and the the current logic level at that pin in order for the device to instruction that invokes power-down is the last instruction function properly. executed. The on-chip RAM and Special Function Regis-
Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 Protection Type
1 U U U No program lock features 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled 3 P P U Same as mode 2, also verify is disabled 4 P P P Same as mode 3, also external execution is disabled
5
Document Outline Block Diagram Features Description Pin Description VCC GND Port 0 Port 1 Port 2 Port 3 RST ALE/PROG PSEN EA/VPP XTAL1 XTAL2 Oscillator Characteristics Status of External Pins During Idle and Power-down Modes Lock Bit Protection Modes Programming the Flash Programming Interface Flash Programming Modes Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V) Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V) Flash Programming and Verification Characteristics Absolute Maximum Ratings* DC Characteristics AC Characteristics External Program and Data Memory Characteristics External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Float Waveforms(1) Ordering Information
