Datasheet AS6C6264 (Alliance Memory) - 5
| Manufacturer | Alliance Memory |
| Description | 8K x 8 Bit Low Power CMOS SRAM |
| Pages / Page | 13 / 5 — AS6C6264. February 2007. Updated July 2017. 8K X 8 BIT LOW POWER CMOS … |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
AS6C6264. February 2007. Updated July 2017. 8K X 8 BIT LOW POWER CMOS SRAM. AC ELECTRICAL CHARACTERISTICS. (1) READ CYCLE
Model Line for this Datasheet
Text Version of Document
AS6C6264 February 2007 Updated July 2017 ® 8K X 8 BIT LOW POWER CMOS SRAM AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER SYM. AS6C6264-55 UNIT MIN. MAX.
Read Cycle Time tRC 55 - ns Address Access Time tAA - 55 ns Chip Enable Access Time tACE - 55 ns Output Enable Access Time tOE 30 ns Chip Enable to Output in Low-Z tCLZ* 10 - ns Output Enable to Output in Low-Z tOLZ* 5 - ns Chip Disable to Output in High-Z tCHZ* - 20 ns Output Disable to Output in High-Z tOHZ* 20 ns Output Hold from Address Change tOH 10 - ns
(2) WRITE CYCLE PARAMETER SYM. AS6C6264-55 UNIT MIN. MAX.
Write Cycle Time tWC 55 - ns Address Valid to End of Write tAW 50 - ns Chip Enable to End of Write tCW 50 - ns Address Set-up Time tAS 0 - ns Write Pulse Width tWP 45 - ns Write Recovery Time tWR 0 - ns Data to Write Time Overlap tDW 25 - ns Data Hold from End of Write Time tDH 0 - ns Output Active from End of Write tOW* 5 - ns Write to Output in High-Z tWHZ* - 20 ns *These parameters are guaranteed by device characterization, but not production tested.
Page 4 of 12 July 2017, v2.0 Alliance Memory Inc
Read Cycle Time tRC 55 - ns Address Access Time tAA - 55 ns Chip Enable Access Time tACE - 55 ns Output Enable Access Time tOE 30 ns Chip Enable to Output in Low-Z tCLZ* 10 - ns Output Enable to Output in Low-Z tOLZ* 5 - ns Chip Disable to Output in High-Z tCHZ* - 20 ns Output Disable to Output in High-Z tOHZ* 20 ns Output Hold from Address Change tOH 10 - ns
(2) WRITE CYCLE PARAMETER SYM. AS6C6264-55 UNIT MIN. MAX.
Write Cycle Time tWC 55 - ns Address Valid to End of Write tAW 50 - ns Chip Enable to End of Write tCW 50 - ns Address Set-up Time tAS 0 - ns Write Pulse Width tWP 45 - ns Write Recovery Time tWR 0 - ns Data to Write Time Overlap tDW 25 - ns Data Hold from End of Write Time tDH 0 - ns Output Active from End of Write tOW* 5 - ns Write to Output in High-Z tWHZ* - 20 ns *These parameters are guaranteed by device characterization, but not production tested.
Page 4 of 12 July 2017, v2.0 Alliance Memory Inc
