Datasheet AD9731 (Analog Devices) - 3

AD9731 SPECIFICATIONS Test Parameter Temp Level Min Typ Max Unit
SFDR PERFORMANCE (Narrowband)13 2 MHz; 2 MHz Span 25∞C V 79 dB 25 MHz, 2 MHz Span 25∞C V 61 dB 10 MHz, 5 MHz Span (Clock = 170 MHz) 25∞C V 73 dB INTERMODULATION DISTORTION14 F1 = 800 kHz, F2 = 900 kHz 25∞C V 58 dB POWER SUPPLY15 Digital –V Supply Current 25∞C I 27 37 mA Full VI 27 42 mA Analog –V Supply Current 25∞C I 45 53 mA Full VI 45 66 mA Digital +V Supply Current 25∞C I 13 20 mA
OBSOLETE
Full VI 15 22 mA Power Dissipation 25∞C V 439 mW Full V 449 mW PSRR 25∞C V 100 mA/V NOTES 1Measured as an error in ratio of full-scale current to current through R SET (640 mA nominal); ratio is nominally 32. DAC load is virtual ground. 2Internal reference voltage is tested under load conditions specified in Internal Reference Output current specification. 3Internal reference output current defines load conditions applied during Internal Reference Voltage test. 4Full-scale current variations among devices are higher when driving REFERENCE IN directly. 5Frequency at which a 3 dB change in output of DAC is observed; RL = 50 W; 100 mV modulation at midscale. 6Based on IFS = 32 (CONTROL AMP IN/RSET) when using internal control amplifier. DAC load is virtual ground. 7Measured as voltage settling at midscale transition to ±0.5 LSB, RL = 50 W. 8Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal. 9Peak glitch impulse is measured as the largest area under a single positive or negative transient. 10Measured with RL = 50 W and DAC operating in latched mode. 11Data must remain stable for specified time prior to rising edge of CLOCK. 12Data must remain stable for specified time after rising edge of CLOCK. 13SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst-case spurious frequencies in the output spectrum window. The frequency span is dc-to-Nyquist unless otherwise noted. 14Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products created will manifest themselves at (2F2–F1) and (2F1–F2) of the two tones. 15Supply voltages should remain stable within ±5% for nominal operation. Specifications subject to change without notice.
pwMIN pwMAX CLOCK tS tH CODE 1 CODE 2 CODE 3 CODE 4 DATA DATA DATA DATA DATA CODE 2 CODE 4 ANALOG OUTPUT CODE 1 CODE 3 DETAIL OF SETTLING TIME GLITCH AREA = 1/2 HEIGHT
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WIDTH CLOCK SPECIFIED ERROR BAND H tPD ANALOG OUTPUT W tST
Figure 1. Timing Diagrams REV. B –3– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION Typical Performance Characteristics THEORY AND APPLICATIONS Digital Inputs/Timing Input Clock and Data Timing Relationship References Analog Output EVALUATION BOARD OUTLINE DIMENSIONS Revision History