Datasheet MP1542 (Monolithic Power Systems) - 9

MP1542 – 700KHz/1.3MHz BOOST CONVERTER WITH A 2A SWITCH Compensation Table 1—Component Selection
The output of the transconductance error amplifier (COMP) is used to compensate the
VIN VOUT C2 R3 C3
regulation control system. The system uses two
(V) (V) (µF) (kΩ) (nF)
poles and one zero to stabilize the control loop. 3.3 8 4.7 10 2.2 The poles are fP1 set by the output capacitor C2 3.3 8 10 10 2.2 and load resistance and fP2 set by the 3.3 8 22 10 2.2 compensation capacitor C3. The zero fZ1 is set by the compensation capacitor C3 and the 3.3 12 4.7 15 1 compensation resistor R3. These are 3.3 12 10 15 1 determined by the equations: 3.3 12 22 15 2.2 3.3 18 4.7 20 1 1 f = 1 P π × C2 × R 3.3 18 10 20 1 LOAD 3.3 18 22 30 2.2 GEA f = 5 8 4.7 10 4.7 P2 2 × π × C3 × A VEA 5 8 10 10 4.7 1 5 8 22 15 1 f = 1 Z 2 × π × C3 × R3 5 12 4.7 15 2.2 5 12 10 15 2.2 Where RLOAD is the load resistance, GEA is the 5 12 22 20 1 error amplifier transconductance, and AVEA is the error amplifier voltage gain. 5 18 4.7 20 1 5 18 10 20 1 The DC loop gain is: 5 18 22 30 1 1.5 × A × × × VEA IN V R LOAD FB V 12 15 4.7 10 2.2 A = VDC 2 12 15 10 10 2.2 OUT V 12 15 22 15 1 Where VFB is the feedback regulation threshold. 12 18 4.7 5.1 2.2 There is also a right-half-plane zero (fRHPZ) that 12 18 10 5.1 2.2 exists in continuous conduction mode (inductor 12 18 22 15 1 current does not drop to zero on each cycle) step-up converters. The frequency of the right half plane zero is: For faster control loop and better transient response, set the capacitor C3 to the 2 V × recommended value in Table 1. Then slowly IN R LOAD f = RHPZ 2 2× π×L × increase the resistor R3 and check the load OUT V step response on a bench to make sure the Table 1 lists generally recommended ringing and overshoot on the output voltage at compensation components for different input the edge of the load steps is minimal. Finally, voltage, output voltage and capacitance of most the compensation needs to be checked by frequently used output ceramic capacitors. calculating the DC loop gain and the crossover Ceramic capacitors have extremely low ESR, frequency. The crossover frequency where the therefore the second compensation capacitor loop gain drops to 0dB or a gain of 1 can be (from COMP to GND) is not required. obtained visually by placing a –20dB/decade slope at each pole, and a +20dB/decade slope at each zero. The crossover frequency should be at least one decade below the frequency of the right-half-plane zero at maximum output load current to obtain high enough phase margin for stability. MP1542 Rev. 1.5 www.MonolithicPower.com
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