Datasheet TLV9061, TLV9062, TLV9064 (Texas Instruments) - 7
| Manufacturer | Texas Instruments |
| Description | 10-MHz, RRIO, CMOS Operational Amplifiers For Cost-Sensivite Systems |
| Pages / Page | 82 / 7 — TLV9061,. TLV9062,. TLV9064. www.ti.com. TLV9061S DBV Package. 6-Pin … |
| File Format / Size | PDF / 5.9 Mb |
| Document Language | English |
TLV9061,. TLV9062,. TLV9064. www.ti.com. TLV9061S DBV Package. 6-Pin SOT-23. Top View. Pin Functions: TLV9061S. PIN. I/O. DESCRIPTION. NAME. NO
Model Line for this Datasheet
Text Version of Document
link to page 25
TLV9061, TLV9062, TLV9064 www.ti.com
SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
TLV9061S DBV Package 6-Pin SOT-23 Top View
OUT 1 6 V+ V 2 ± 5 SHDN +IN 3 4 ±IN Not to scale
Pin Functions: TLV9061S PIN I/O DESCRIPTION NAME NO.
IN– 4 I Inverting input IN+ 3 I Noninverting input OUT 1 O Output Shutdown: low = amp disabled, high = amp enabled. See Shutdown Function section for SHDN 5 I more information. V– 2 I or — Negative (low) supply or ground (for single-supply operation) V+ 6 I Positive (high) supply
TLV9062 D, DGK, PW, DDF Packages 8-Pin SOIC, VSSOP, TSSOP, SOT-23 TLV9062 DSG Package Top View 8-Pin WSON With Exposed Thermal Pad Top View
OUT1 1 8 V+ OUT1 1 8 V+ IN1 2 ± 7 OUT2 IN1 2 ± 7 OUT2 IN1+ 3 6 IN2± Thermal Pad IN1+ 3 6 IN2± V 4 ± 5 IN2+ V 4 ± 5 IN2+ Not to scale Not to scale (1) Connect thermal pad to V–
Pin Functions: TLV9062 PIN I/O DESCRIPTION NAME NO.
IN1– 2 I Inverting input, channel 1 IN1+ 3 I Noninverting input, channel 1 IN2– 6 I Inverting input, channel 2 IN2+ 5 I Noninverting input, channel 2 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 V– 4 — Negative (lowest) supply or ground (for single-supply operation) V+ 8 — Positive (highest) supply Copyright © 2017–2019, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TLV9061 TLV9062 TLV9064 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Description (continued) 6 Device Comparison Table 7 Pin Configuration and Functions 8 Specifications 8.1 Absolute Maximum Ratings 8.2 ESD Ratings 8.3 Recommended Operating Conditions 8.4 Thermal Information: TLV9061 8.5 Thermal Information: TLV9061S 8.6 Thermal Information: TLV9062 8.7 Thermal Information: TLV9062S 8.8 Thermal Information: TLV9064 8.9 Thermal Information: TLV9064S 8.10 Electrical Characteristics 8.11 Typical Characteristics 9 Detailed Description 9.1 Overview 9.2 Functional Block Diagram 9.3 Feature Description 9.3.1 Rail-to-Rail Input 9.3.2 Rail-to-Rail Output 9.3.3 EMI Rejection 9.3.4 Overload Recovery 9.3.5 Shutdown Function 9.4 Device Functional Modes 10 Application and Implementation 10.1 Application Information 10.2 Typical Applications 10.2.1 Typical Low-Side Current Sense Application 10.2.1.1 Design Requirements 10.2.1.2 Detailed Design Procedure 10.2.1.3 Application Curve 11 Power Supply Recommendations 11.1 Input and ESD Protection 12 Layout 12.1 Layout Guidelines 12.2 Layout Example 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation 13.2 Related Links 13.3 Receiving Notification of Documentation Updates 13.4 Community Resources 13.5 Trademarks 13.6 Electrostatic Discharge Caution 13.7 Glossary 14 Mechanical, Packaging, and Orderable Information
TLV9061, TLV9062, TLV9064 www.ti.com
SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
TLV9061S DBV Package 6-Pin SOT-23 Top View
OUT 1 6 V+ V 2 ± 5 SHDN +IN 3 4 ±IN Not to scale
Pin Functions: TLV9061S PIN I/O DESCRIPTION NAME NO.
IN– 4 I Inverting input IN+ 3 I Noninverting input OUT 1 O Output Shutdown: low = amp disabled, high = amp enabled. See Shutdown Function section for SHDN 5 I more information. V– 2 I or — Negative (low) supply or ground (for single-supply operation) V+ 6 I Positive (high) supply
TLV9062 D, DGK, PW, DDF Packages 8-Pin SOIC, VSSOP, TSSOP, SOT-23 TLV9062 DSG Package Top View 8-Pin WSON With Exposed Thermal Pad Top View
OUT1 1 8 V+ OUT1 1 8 V+ IN1 2 ± 7 OUT2 IN1 2 ± 7 OUT2 IN1+ 3 6 IN2± Thermal Pad IN1+ 3 6 IN2± V 4 ± 5 IN2+ V 4 ± 5 IN2+ Not to scale Not to scale (1) Connect thermal pad to V–
Pin Functions: TLV9062 PIN I/O DESCRIPTION NAME NO.
IN1– 2 I Inverting input, channel 1 IN1+ 3 I Noninverting input, channel 1 IN2– 6 I Inverting input, channel 2 IN2+ 5 I Noninverting input, channel 2 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 V– 4 — Negative (lowest) supply or ground (for single-supply operation) V+ 8 — Positive (highest) supply Copyright © 2017–2019, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TLV9061 TLV9062 TLV9064 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Description (continued) 6 Device Comparison Table 7 Pin Configuration and Functions 8 Specifications 8.1 Absolute Maximum Ratings 8.2 ESD Ratings 8.3 Recommended Operating Conditions 8.4 Thermal Information: TLV9061 8.5 Thermal Information: TLV9061S 8.6 Thermal Information: TLV9062 8.7 Thermal Information: TLV9062S 8.8 Thermal Information: TLV9064 8.9 Thermal Information: TLV9064S 8.10 Electrical Characteristics 8.11 Typical Characteristics 9 Detailed Description 9.1 Overview 9.2 Functional Block Diagram 9.3 Feature Description 9.3.1 Rail-to-Rail Input 9.3.2 Rail-to-Rail Output 9.3.3 EMI Rejection 9.3.4 Overload Recovery 9.3.5 Shutdown Function 9.4 Device Functional Modes 10 Application and Implementation 10.1 Application Information 10.2 Typical Applications 10.2.1 Typical Low-Side Current Sense Application 10.2.1.1 Design Requirements 10.2.1.2 Detailed Design Procedure 10.2.1.3 Application Curve 11 Power Supply Recommendations 11.1 Input and ESD Protection 12 Layout 12.1 Layout Guidelines 12.2 Layout Example 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation 13.2 Related Links 13.3 Receiving Notification of Documentation Updates 13.4 Community Resources 13.5 Trademarks 13.6 Electrostatic Discharge Caution 13.7 Glossary 14 Mechanical, Packaging, and Orderable Information
