Datasheet SiC931 (Vishay) - 6

ManufacturerVishay
Description4.5 V to 18 V Input, 20 A MicroBRICK DC/DC Regulator Module
Pages / Page22 / 6 — SiC931. OPERATIONAL DESCRIPTION Device Overview. Fig. 6 - VM-COT Block …
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SiC931. OPERATIONAL DESCRIPTION Device Overview. Fig. 6 - VM-COT Block Diagram. Power Stage. Control Mechanism

SiC931 OPERATIONAL DESCRIPTION Device Overview Fig 6 - VM-COT Block Diagram Power Stage Control Mechanism

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SiC931
www.vishay.com Vishay Siliconix
OPERATIONAL DESCRIPTION Device Overview
SiC931 is a high efficiency synchronous buck regulator VIN capable of delivering up to 20 A continuous current. The L VOUT device has user programmable switching frequency of SW R1 600 kHz, 1 MHz, 1.5 MHz, and 2 MHz. The control scheme C R C X X Y FB C Load OUT delivers fast transient response and minimizes the number VIN Ramp R2 of external components. Thanks to the internal ramp COMP Error Amp Ripple based information, no high ESR output bulk or virtual ESR network controller Ref RC is required for the loop stability. This device also CC SiC931 incorporates a power saving feature that enables diode emulation mode and frequency fold back as the load decreases. SiC931 has a full set of protection and monitoring features:
Fig. 6 - VM-COT Block Diagram
• Over current protection in pulse-by-pulse mode All components for RAMP signal generation and error • Output over voltage protection amplifier compensation required for the control loop are • Output under voltage protection with device latch internal to the IC, see Fig. 6. In order for the device to cover • Over temperature protection with hysteresis a wide range of VOUT operation, the internal RAMP signal • Dedicated enable pin for easy power sequencing components (RX, CX, CY) are automatically selected • Power good open drain output depending on the VOUT voltage and switching frequency. This device is available in MLP60-A6C package to deliver This method allows the RAMP amplitude to remain constant high power density and minimize PCB area. throughout the VOUT voltage range, achieving low jitter and fast transient Response. The error amplifier internal
Power Stage
compensation consists of a resistor in series with a SiC931 integrates a high performance power stage with capacitor (RCOMP, CCOMP). both high side and low side MOSFETs and a 220 nH output Fig. 7 demonstrates the basic operational waveforms: inductor. The power stage is optimized to achieve up to 95 % efficiency with 1.5 MHz switching frequency. The input voltage (VIN) can go up to 18 V and down to as low VRAMP as 4.5 V for power conversion. An internal LDO converts input voltage from VCIN to VDD for controller and driver power supply. There is no need to connect an external 5 V bias. VCOMP
Control Mechanism
SiC931 employs an advanced voltage - mode COT control mechanism. During steady-state operation, feedback voltage (VFB) is compared with internal reference (0.6 V typ.) PWM and the amplified error signal (VCOMP) is generated at the Fixed on-time internal comp node. An internally generated ramp signal and
Fig. 7 - VM-COT Operational Principle
VCOMP feed into a comparator. Once VRAMP crosses VCOMP, an on-time pulse is generated for a fixed time. During the
Light Load Condition
on-time pulse, the high side MOSFET will be turned on. To improve efficiency at light-load condition, SiC931 Once the on-time pulse expires, the low side MOSFET will provides a set of innovative implementations to eliminate LS be turned on after a dead time period. The low side MOSFET recirculating current and switching losses. The internal zero will stay on for a minimum duration equal to the minimum crossing detector monitors SW node voltage to determine off-time (tOFF_MIN.) and remains on until VRAMP crosses when inductor current starts to flow negatively. In power VCOMP. The cycle is then repeated. saving mode, as soon as inductor valley current crosses Fig. 6 illustrates the basic block diagram for VM-COT zero, the device deploys diode emulation mode by turning architecture. In this architecture the following is achieved: off low side MOSFET. If load further decreases, switching frequency is reduced proportional to load condition to save • The reference of a basic ripple control regulator is replaced with a high again error amplifier loop switching losses while keeping output ripple within • This establishes two parallel voltage regulating feedback tolerance. The switching frequency is set by the controller to paths, a fast and slow path maintain regulation. There is no minimum switching • Fast path is the ripple injection which ensures rapid frequency limitation. correction of the transient perturbation • Slow path is the error amplifier loop which ensures the DC component of the output voltage follows the internal accurate reference voltage S23-0880-Rev. G, 23-Oct-2023
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