Datasheet MAX20480 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Four- to Seven-Input Automotive Power- System Monitor Family |
| Pages / Page | 41 / 5 — Electrical Characteristics (continued). PARAMETER. SYMBOL. CONDITIONS. … |
| File Format / Size | PDF / 575 Kb |
| Document Language | English |
Electrical Characteristics (continued). PARAMETER. SYMBOL. CONDITIONS. MIN. TYP. MAX. UNITS. ADDR, EN0, EN1 INPUTS
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Text Version of Document
MAX20480 Four- to Seven-Input Automotive Power-System Monitor Family
Electrical Characteristics (continued)
(VDD = 3.3V, TA = TJ = -40°C to +125°C, unless otherwise noted, Typical values are at TA = 25°C under normal conditions unless otherwise noted., )
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
(IN6P, IN7P) voltage falling, relative to 0.23 0.25 0.27 INM OFF Threshold VOFF V (IN6P, IN7P) voltage rising, relative to 0.28 0.3 0.32 INM UV Comparator Filter t Time UV 2% below threshold 5 µs OV Comparator Filter t Time OV 2% above threshold 5 µs
ADDR, EN0, EN1 INPUTS
Input High Level VIH Input Voltage Rising 1.3 V Input Low Level VIL Input Voltage Falling 0.4 V Hysteresis 0.1 V EN0, EN1 Pulldown R Resistance PD VEN0 = VEN1 = 3.3V 1.1 2 3 MΩ EN0, EN1 Spike 60 ns Suppression ADDR Input Leakage IADDR-LKG VADDR = VDD = 3.3V 1 µA
DIGITAL OUTPUT (RESET)
Digital Output Low Level VRL VDD = 2.35V, ISINK = 2mA 0.2 V Digital Output Leakage IR-LKG RESET = 5.0V 1 µA RHLD[1:0] = 00 6 μs RHLD[1:0] = 01 7.2 8 8.8 Active Timeout Period tHOLD RHLD[1:0] = 10 14.4 16 17.6 ms RHLD[1:0] = 11 28.8 32 35.2
I2C INTERFACE
Input High Level VIH Input Voltage Rising 1.3 V Input Low Level VIL Input Voltage Falling 0.4 V Output Low VOL ISINK = 4mA 0.3 V Input Leakage ILKG VSCL = VSDA = 3.3V 1 μA Clock Frequency fSCL 1.1 MHz Setup Time (Repeated) t START SU:STA 260 ns Hold Time (Repeated) t START HD:STA 260 ns SCL Low Time tLOW 350 ns SCL High Time tHIGH 260 ns Data Setup Time tSU:DAT 150 ns Data Hold Time tHD:DAT 30 ns Setup Time for STOP t Condition SU:STO 260 ns www.maximintegrated.com Maxim Integrated | 5 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 16-TQFN-EP Electrical Characteristics Electrical Characteristics (continued) Typical Operating Characteristics Typical Operating Characteristics (continued) Pin Configurations MAX20480A MAX20480B MAX20480C MAX20480D Pin Description Pin Description (continued) Functional Diagram Detailed Description I2C Interface Bit Transfer STOP and START Conditions Early STOP Condition Clock Stretching I2C General Call Address Packet Error Checking (PEC) Slave Address Acknowledge Write-Data Format Read-Data Format Voltage Monitor DVS Operation DVS Command Sequence (Low to High): DVS Command Sequence (High to Low): I2C DVS Timing Example (Low to High) Flexible Power Sequence Recorder Windowed Watchdog and Reset Control Sample C Code For Challenge/Response Watchdog Window Settings RESET Output Enable Inputs (EN0/EN1) Comparator Power States Register Map Top Level Register Details ID (0x00) CONFIG1 (0x01) CONFIG2 (0x02) VMON (0x03) RSTMAP (0x4) STATOV (0x5) STATUV (0x6) STATOFF (0x7) VIN1 (0x8) VIN2 (0x9) VIN3 (0xA) VIN4 (0xB) VIN5 (0xC) VINO6 (0xD) VINU6 (0xE) VINO7 (0xF) VINU7 (0x10) OVUV1 (0x11) OVUV2 (0x12) OVUV3 (0x13) OVUV4 (0x14) OVUV5 (0x15) FPSSTAT1 (0x16) FPSCFG1 (0x17) UTIME1 (0x18) UTIME2 (0x19) UTIME3 (0x1A) UTIME4 (0x1B) UTIME5 (0x1C) UTIME6 (0x1D) UTIME7 (0x1E) DTIME1 (0x1F) DTIME2 (0x20) DTIME3 (0x21) DTIME4 (0x22) DTIME5 (0x23) DTIME6 (0x24) DTIME7 (0x25) WDSTAT (0x26) WDCDIV (0x27) WDCFG1 (0x28) WDCFG2 (0x29) WDKEY (0x2A) WDLOCK (0x2B) RSTCTRL (0x2C) CID (0x2D) Applications Information Diagnostics Typical Application Circuit Ordering Information Revision History
Electrical Characteristics (continued)
(VDD = 3.3V, TA = TJ = -40°C to +125°C, unless otherwise noted, Typical values are at TA = 25°C under normal conditions unless otherwise noted., )
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
(IN6P, IN7P) voltage falling, relative to 0.23 0.25 0.27 INM OFF Threshold VOFF V (IN6P, IN7P) voltage rising, relative to 0.28 0.3 0.32 INM UV Comparator Filter t Time UV 2% below threshold 5 µs OV Comparator Filter t Time OV 2% above threshold 5 µs
ADDR, EN0, EN1 INPUTS
Input High Level VIH Input Voltage Rising 1.3 V Input Low Level VIL Input Voltage Falling 0.4 V Hysteresis 0.1 V EN0, EN1 Pulldown R Resistance PD VEN0 = VEN1 = 3.3V 1.1 2 3 MΩ EN0, EN1 Spike 60 ns Suppression ADDR Input Leakage IADDR-LKG VADDR = VDD = 3.3V 1 µA
DIGITAL OUTPUT (RESET)
Digital Output Low Level VRL VDD = 2.35V, ISINK = 2mA 0.2 V Digital Output Leakage IR-LKG RESET = 5.0V 1 µA RHLD[1:0] = 00 6 μs RHLD[1:0] = 01 7.2 8 8.8 Active Timeout Period tHOLD RHLD[1:0] = 10 14.4 16 17.6 ms RHLD[1:0] = 11 28.8 32 35.2
I2C INTERFACE
Input High Level VIH Input Voltage Rising 1.3 V Input Low Level VIL Input Voltage Falling 0.4 V Output Low VOL ISINK = 4mA 0.3 V Input Leakage ILKG VSCL = VSDA = 3.3V 1 μA Clock Frequency fSCL 1.1 MHz Setup Time (Repeated) t START SU:STA 260 ns Hold Time (Repeated) t START HD:STA 260 ns SCL Low Time tLOW 350 ns SCL High Time tHIGH 260 ns Data Setup Time tSU:DAT 150 ns Data Hold Time tHD:DAT 30 ns Setup Time for STOP t Condition SU:STO 260 ns www.maximintegrated.com Maxim Integrated | 5 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 16-TQFN-EP Electrical Characteristics Electrical Characteristics (continued) Typical Operating Characteristics Typical Operating Characteristics (continued) Pin Configurations MAX20480A MAX20480B MAX20480C MAX20480D Pin Description Pin Description (continued) Functional Diagram Detailed Description I2C Interface Bit Transfer STOP and START Conditions Early STOP Condition Clock Stretching I2C General Call Address Packet Error Checking (PEC) Slave Address Acknowledge Write-Data Format Read-Data Format Voltage Monitor DVS Operation DVS Command Sequence (Low to High): DVS Command Sequence (High to Low): I2C DVS Timing Example (Low to High) Flexible Power Sequence Recorder Windowed Watchdog and Reset Control Sample C Code For Challenge/Response Watchdog Window Settings RESET Output Enable Inputs (EN0/EN1) Comparator Power States Register Map Top Level Register Details ID (0x00) CONFIG1 (0x01) CONFIG2 (0x02) VMON (0x03) RSTMAP (0x4) STATOV (0x5) STATUV (0x6) STATOFF (0x7) VIN1 (0x8) VIN2 (0x9) VIN3 (0xA) VIN4 (0xB) VIN5 (0xC) VINO6 (0xD) VINU6 (0xE) VINO7 (0xF) VINU7 (0x10) OVUV1 (0x11) OVUV2 (0x12) OVUV3 (0x13) OVUV4 (0x14) OVUV5 (0x15) FPSSTAT1 (0x16) FPSCFG1 (0x17) UTIME1 (0x18) UTIME2 (0x19) UTIME3 (0x1A) UTIME4 (0x1B) UTIME5 (0x1C) UTIME6 (0x1D) UTIME7 (0x1E) DTIME1 (0x1F) DTIME2 (0x20) DTIME3 (0x21) DTIME4 (0x22) DTIME5 (0x23) DTIME6 (0x24) DTIME7 (0x25) WDSTAT (0x26) WDCDIV (0x27) WDCFG1 (0x28) WDCFG2 (0x29) WDKEY (0x2A) WDLOCK (0x2B) RSTCTRL (0x2C) CID (0x2D) Applications Information Diagnostics Typical Application Circuit Ordering Information Revision History
