Datasheet L99H92 (STMicroelectronics) - 7
| Manufacturer | STMicroelectronics |
| Description | Half-Bridge Pre-Driver For Automotive Applications |
| Pages / Page | 77 / 7 — L99H92. Standby mode (EN). 2.1.4. VDD overvoltage (VDDOV). 2.1.5. Digital … |
| File Format / Size | PDF / 4.2 Mb |
| Document Language | English |
L99H92. Standby mode (EN). 2.1.4. VDD overvoltage (VDDOV). 2.1.5. Digital input/output overvoltage (DIOOV). 2.1.6
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L99H92 Standby mode (EN) 2.1.4 VDD overvoltage (VDDOV)
When the VDD exceeds the VDDOV threshold for a time longer than tovuv_filt, then the corresponding overvoltage flag (VDDOV) is set, and to protect the application all the gate drivers are forced in sink switch mode to switch off actively all the MOSFETs with the maximum available current, regardless of the programmed gate discharge current (SLEWDx control bits). The gate drivers come out of forced sink switch mode once the overvoltage flag VDDOV is cleared. The overvoltage flag VDDOV can be cleared by an SPI “Read & Clear” command only if the VDD overvoltage condition is no longer present, namely if VDD<VDDOV for a time longer than the corresponding filtering time tovuv_filt. The VDD overvoltage protection aims at making the application robust against VDD short to battery.
2.1.5 Digital input/output overvoltage (DIOOV)
When the voltage at any of the digital input/output pins listed below exceeds the VDIOOV threshold for a time longer than tovuv_filt, then the corresponding overvoltage flag (DIOOV) is set, and to protect the application all the gate drivers are forced in sink switch mode to switch off actively all the MOSFETs with the maximum available current, regardless of the programmed gate discharge current (SLEWDx control bits). The gate drivers come out of forced sink switch mode once the overvoltage flag DIOOV is cleared. The overvoltage flag DIOOV can be cleared by an SPI “Read & Clear” command only if the digital input/output overvoltage condition is no longer present namely if VDIO<VDIOOV for a time longer than the corresponding filtering time tovuv_filt. The digital input/ output overvoltage protection aims to make the application robust against digital input/output pins short to battery. The digital input/output pins monitored for overvoltage events are: PWM/IN1, DIR/IN2, DIAGN, CSO1, CSO2, CSN, SDI, SDO, CLK. Any overvoltage detection affecting the device digital output pins DIAGN and SDO will not affect/propagate internally to VDD. Anyhow, all the digital input/output pins, FSINB pin and EN pin included, can withstand a short to battery up to the related absolute maximum rating (see Table 17).
2.1.6 Power-on reset (POR)
The device gets out of standby mode to get into active mode as soon as the EN pin is high, the VDD is above VDDPOR_OFF and the VS is above VSPOR_OFF. If either the VDD falls below VDDPOR_ON or the VS falls below VSPOR_ON with the EN pin still high, the device experiences a power-on reset and enter in standby mode. In standby mode the gate drivers and the charge pump are switched off, leaving just the internal resistive link between gate and source at each MOSFET (RGSHx and RGSLx). Besides, the content of all the registers is reset to default value. Once out of standby mode the global status byte RSTB bit will be set indicating that all the device registers have been reset to default value. This bit is automatically cleared by any valid SPI communication frame.
2.2 Standby mode (EN)
The L99H92 is enabled/disabled by pulling the EN input pin high/low. If VDD > VDDPOR_OFF, VS>VSPOR_OFF and EN input pin is high, the device enters in active mode. If any of the above conditions is not met, the device will remain in standby mode. When the EN input pin is left floating, because of the internal pull-down current (IIN), the device enters (if not already) in standby mode minimizing its current consumption. In standby mode the minimum current drawn by VS, less than 5 μA (ISq) for CSN = high (SDO in tristate), can be achieved by pulling the EN input pin low. Besides, in standby mode, the gate drivers together with the charge pump are switched off. All the MOSFETs are passively switched off by the internal resistive link between gate and source present at each MOSFET (regardless of the control input pins PWM/IN1, DIR/IN2 and FSINB logic levels), and all the registers are reset to default values. Out of standby mode the device diagnostic is available and all the operations on the device registers are available as well.
2.3 Active mode (OUTE)
As soon as the EN pin is high, the VDD is above VDDPOR_OFF and the VS is above VSPOR_OFF the device comes out of standby mode to go in active mode. In active mode the device diagnostic is available. In active mode with no faults, the charge pump is enabled, and the gate drivers are enabled as long as the OUTE control bit is set. Instead, if the OUTE control bit is reset, then all the gate drivers are disabled and all the MOSFETs are switched off passively through the internal resistive connection between gate and source present at each MOSFET. In active mode with no fault and with OUTE set, the MOSFETs to be turned on are controlled through the combination of the input signals PWM/IN1, DIR/IN2 and the control bits INPMODE, AFWE and FWS.
DS14069
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Rev 4 page 7/77
Document Outline L99H92 Features Applications Description 1 Block diagram and pins description 1.1 Block diagram 1.2 Pinout 1.3 Pins description 2 Device description 2.1 Supply pins 2.1.1 VS overvoltage warning (VSOVW) 2.1.2 VDH overvoltage (VDHOV) 2.1.3 VDH undervoltage (VDHUV) 2.1.4 VDD overvoltage (VDDOV) 2.1.5 Digital input/output overvoltage (DIOOV) 2.1.6 Power-on reset (POR) 2.2 Standby mode (EN) 2.3 Active mode (OUTE) 2.4 Thermal warning and thermal shutdown (TW/TSD) 2.5 Charge pump (CPOUT) 2.6 Gate drivers 2.6.1 Outputs driving signals (PWM/IN1 and DIR/IN2) 2.6.2 Slew rate control (SLEW) 2.6.3 Short circuit detection / drain-source monitoring (DSHS/DSLS) 2.6.4 Programmable cross current protection time (DT) 2.7 Diagnostic in off-mode (O1DS/O2DS) 2.8 Fail-safe output switch-off input not pin (FSINB) 2.9 Diagnostic not output (DIAGN) 2.10 Current monitors 2.11 Window watchdog (WDG) 3 Application 4 Serial peripheral interface (SPI) 4.1 ST SPI 4.1 4.1.1 Physical layer 4.1.2 Clock and data characteristics 4.1.3 Communication protocol 4.1.4 Address definition 5 Electrical characteristics 5.1 Absolute maximum ratings 5.2 ESD protection 5.3 Thermal data 5.4 Electrical characteristics 5.4.1 Supply, supply monitoring 5.4.2 Power-on reset 5.5 Charge pump 5.6 Full-bridge driver 5.7 VDS monitoring thresholds 5.7.1 Open-load monitoring external full-bridges 5.8 Current sense amplifiers (CSA) 5.9 Fail-safe switch-off input FSINB 5.10 Enable 5.11 DIAGN 5.12 Watchdog 5.13 SPI electrical characteristics 5.14 Oscillator 5.15 Operating modes 6 SPI registers 6.1 Global status byte GSB 6.2 Register map overview 6.3 Status registers 6.4 Control registers 7 Package information 7.1 QFN32L 5x5 mm package information 7.2 TQFP32L 7x7 mm package information Revision history
L99H92 Standby mode (EN) 2.1.4 VDD overvoltage (VDDOV)
When the VDD exceeds the VDDOV threshold for a time longer than tovuv_filt, then the corresponding overvoltage flag (VDDOV) is set, and to protect the application all the gate drivers are forced in sink switch mode to switch off actively all the MOSFETs with the maximum available current, regardless of the programmed gate discharge current (SLEWDx control bits). The gate drivers come out of forced sink switch mode once the overvoltage flag VDDOV is cleared. The overvoltage flag VDDOV can be cleared by an SPI “Read & Clear” command only if the VDD overvoltage condition is no longer present, namely if VDD<VDDOV for a time longer than the corresponding filtering time tovuv_filt. The VDD overvoltage protection aims at making the application robust against VDD short to battery.
2.1.5 Digital input/output overvoltage (DIOOV)
When the voltage at any of the digital input/output pins listed below exceeds the VDIOOV threshold for a time longer than tovuv_filt, then the corresponding overvoltage flag (DIOOV) is set, and to protect the application all the gate drivers are forced in sink switch mode to switch off actively all the MOSFETs with the maximum available current, regardless of the programmed gate discharge current (SLEWDx control bits). The gate drivers come out of forced sink switch mode once the overvoltage flag DIOOV is cleared. The overvoltage flag DIOOV can be cleared by an SPI “Read & Clear” command only if the digital input/output overvoltage condition is no longer present namely if VDIO<VDIOOV for a time longer than the corresponding filtering time tovuv_filt. The digital input/ output overvoltage protection aims to make the application robust against digital input/output pins short to battery. The digital input/output pins monitored for overvoltage events are: PWM/IN1, DIR/IN2, DIAGN, CSO1, CSO2, CSN, SDI, SDO, CLK. Any overvoltage detection affecting the device digital output pins DIAGN and SDO will not affect/propagate internally to VDD. Anyhow, all the digital input/output pins, FSINB pin and EN pin included, can withstand a short to battery up to the related absolute maximum rating (see Table 17).
2.1.6 Power-on reset (POR)
The device gets out of standby mode to get into active mode as soon as the EN pin is high, the VDD is above VDDPOR_OFF and the VS is above VSPOR_OFF. If either the VDD falls below VDDPOR_ON or the VS falls below VSPOR_ON with the EN pin still high, the device experiences a power-on reset and enter in standby mode. In standby mode the gate drivers and the charge pump are switched off, leaving just the internal resistive link between gate and source at each MOSFET (RGSHx and RGSLx). Besides, the content of all the registers is reset to default value. Once out of standby mode the global status byte RSTB bit will be set indicating that all the device registers have been reset to default value. This bit is automatically cleared by any valid SPI communication frame.
2.2 Standby mode (EN)
The L99H92 is enabled/disabled by pulling the EN input pin high/low. If VDD > VDDPOR_OFF, VS>VSPOR_OFF and EN input pin is high, the device enters in active mode. If any of the above conditions is not met, the device will remain in standby mode. When the EN input pin is left floating, because of the internal pull-down current (IIN), the device enters (if not already) in standby mode minimizing its current consumption. In standby mode the minimum current drawn by VS, less than 5 μA (ISq) for CSN = high (SDO in tristate), can be achieved by pulling the EN input pin low. Besides, in standby mode, the gate drivers together with the charge pump are switched off. All the MOSFETs are passively switched off by the internal resistive link between gate and source present at each MOSFET (regardless of the control input pins PWM/IN1, DIR/IN2 and FSINB logic levels), and all the registers are reset to default values. Out of standby mode the device diagnostic is available and all the operations on the device registers are available as well.
2.3 Active mode (OUTE)
As soon as the EN pin is high, the VDD is above VDDPOR_OFF and the VS is above VSPOR_OFF the device comes out of standby mode to go in active mode. In active mode the device diagnostic is available. In active mode with no faults, the charge pump is enabled, and the gate drivers are enabled as long as the OUTE control bit is set. Instead, if the OUTE control bit is reset, then all the gate drivers are disabled and all the MOSFETs are switched off passively through the internal resistive connection between gate and source present at each MOSFET. In active mode with no fault and with OUTE set, the MOSFETs to be turned on are controlled through the combination of the input signals PWM/IN1, DIR/IN2 and the control bits INPMODE, AFWE and FWS.
DS14069
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Rev 4 page 7/77
Document Outline L99H92 Features Applications Description 1 Block diagram and pins description 1.1 Block diagram 1.2 Pinout 1.3 Pins description 2 Device description 2.1 Supply pins 2.1.1 VS overvoltage warning (VSOVW) 2.1.2 VDH overvoltage (VDHOV) 2.1.3 VDH undervoltage (VDHUV) 2.1.4 VDD overvoltage (VDDOV) 2.1.5 Digital input/output overvoltage (DIOOV) 2.1.6 Power-on reset (POR) 2.2 Standby mode (EN) 2.3 Active mode (OUTE) 2.4 Thermal warning and thermal shutdown (TW/TSD) 2.5 Charge pump (CPOUT) 2.6 Gate drivers 2.6.1 Outputs driving signals (PWM/IN1 and DIR/IN2) 2.6.2 Slew rate control (SLEW) 2.6.3 Short circuit detection / drain-source monitoring (DSHS/DSLS) 2.6.4 Programmable cross current protection time (DT) 2.7 Diagnostic in off-mode (O1DS/O2DS) 2.8 Fail-safe output switch-off input not pin (FSINB) 2.9 Diagnostic not output (DIAGN) 2.10 Current monitors 2.11 Window watchdog (WDG) 3 Application 4 Serial peripheral interface (SPI) 4.1 ST SPI 4.1 4.1.1 Physical layer 4.1.2 Clock and data characteristics 4.1.3 Communication protocol 4.1.4 Address definition 5 Electrical characteristics 5.1 Absolute maximum ratings 5.2 ESD protection 5.3 Thermal data 5.4 Electrical characteristics 5.4.1 Supply, supply monitoring 5.4.2 Power-on reset 5.5 Charge pump 5.6 Full-bridge driver 5.7 VDS monitoring thresholds 5.7.1 Open-load monitoring external full-bridges 5.8 Current sense amplifiers (CSA) 5.9 Fail-safe switch-off input FSINB 5.10 Enable 5.11 DIAGN 5.12 Watchdog 5.13 SPI electrical characteristics 5.14 Oscillator 5.15 Operating modes 6 SPI registers 6.1 Global status byte GSB 6.2 Register map overview 6.3 Status registers 6.4 Control registers 7 Package information 7.1 QFN32L 5x5 mm package information 7.2 TQFP32L 7x7 mm package information Revision history
