Datasheet ICL7660S, ICL7660A (Renesas) - 10

link to page 7 link to page 10 link to page 10 link to page 10 link to page 10 link to page 10 link to page 9 link to page 11 ICL7660S, ICL7660A 0.1µF, can be used in conjunction with the Boost Pin to achieve VF, where V+ is the supply voltage and VF is the forward similar output currents compared to the device free running voltage on C1, plus the supply voltage (V+) is applied through with C1 = C2 = 10µF or 100µF. (see Figure 11). diode D2 to capacitor C2. The voltage thus created on C2 becomes (2V+) - (2V Increasing the oscillator frequency can also be achieved by F) or twice the supply voltage minus the combined forward voltage drops of diodes D overdriving the oscillator from an external clock, as shown in 1 and D2. Figure 16. In order to prevent device latchup, a 1k resistor The source impedance of the output (VOUT) will depend on the must be used in series with the clock output. In a situation output current, but for V+ = 5V and an output current of 10mA, where the designer has generated the external clock frequency it will be approximately 60. using TTL logic, the addition of a 10k pull-up resistor to V+ supply is required. Note that the pump frequency with external
V+
clocking, as with internal clocking, will be one-half of the clock
1 8
frequency. Output transitions occur on the positive going edge
D
of the clock.
2 7 1 ICL7660S 3 ICL7660A 6 D2 VOUT = V+ V+ (2V+) - (2VF) 4 5 + C2 1 8 + - 1k
Ω
C1 CMOS - 2 7 ICL7660S GATE + 10µF 3 ICL7660A 6 - NOTE: D1 AND D2 CAN BE ANY SUITABLE DIODE. 4 5 VOUT - FIGURE 18. POSITIVE VOLTAGE DOUBLER 10µF + Combined Negative Voltage Conversion and Positive Supply Doubling FIGURE 16. EXTERNAL CLOCKING
Figure 19 combines the functions shown in Figure 15 and It is also possible to increase the conversion efficiency of the Figure 18 to provide negative voltage conversion and positive ICL7660S and ICL7660A at low load levels by lowering the voltage doubling simultaneously. This approach would be oscillator frequency. This reduces the switching losses, and is suitable, for example, for generating +9V and -5V from an shown in Figure 17. However, lowering the oscillator frequency existing +5V supply. In this instance, capacitors C1 and C3 will cause an undesirable increase in the impedance of the perform the pump and reservoir functions, respectively, for pump (C negative voltage generation, while capacitors C2 and C4 are 1) and reservoir (C2) capacitors; this is overcome by increasing the values of C pump and reservoir, respectively, for the doubled positive 1 and C2 by the same factor by which the frequency has been reduced. For example, the voltage. There is a penalty in this configuration which addition of a 100pF capacitor between pin 7 (OSC and V+) will combines both functions, however, in that the source lower the oscillator frequency to 1kHz from its nominal impedances of the generated supplies will be somewhat frequency of 10kHz (a multiple of 10), and thereby necessitate higher, due to the finite impedance of the common charge a corresponding increase in the value of C pump driver at pin 2 of the device. 1 and C2 (from 10µF to 100µF).
V+ V+ 1 8 VOUT = -VIN 2 7 - C 1 8 ICL7660S D1 3 + ICL7660A + COSC C1 3 6 2 7 - ICL7660S + 4 5 C ICL7660A 1 3 6 - D2 - + VOUT = (2V+) - 4 5 VOUT - (VFD1) - (VFD2) C C + 2 2 + C4 - D FIGURE 17. LOWERING OSCILLATOR FREQUENCY 3 FIGURE 19. COMBINED NEGATIVE VOLTAGE CONVERTER AND POSITIVE DOUBLER Positive Voltage Doubling
The ICL7660S and ICL7660A may be employed to achieve
Voltage Splitting
positive voltage doubling using the circuit shown in Figure 18. The bidirectional characteristics can also be used to split a In this application, the pump inverter switches of the ICL7660S high supply in half, as shown in Figure 20. The combined load and ICL7660A are used to charge C1 to a voltage level of V+ - will be evenly shared between the two sides, and a high value FN3179 Rev 7.01 Page 10 of 14 Feb 10, 2020