Datasheet DS4303 (Analog Devices) - 6

ManufacturerAnalog Devices
DescriptionElectronically Programmable Voltage Reference
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Electronically Programmable Voltage Reference. Pin Description. Detailed Description. PIN. NAME. FUNCTION. DS4303. Block Diagram

Electronically Programmable Voltage Reference Pin Description Detailed Description PIN NAME FUNCTION DS4303 Block Diagram

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Electronically Programmable Voltage Reference Pin Description Detailed Description
The DS4303 provides a precise, NV output voltage, VOUT, making it an ideal solution for factory calibration
PIN NAME FUNCTION
of embedded systems. The DS4303 output voltage can 1 ADJ Adjust Control Input be adjusted over almost the entire operating supply 2 GND Ground range of the device, and it can be precisely set to with-
DS4303
in ±1mV. A graphical description of the DS4303 is pro- 3 VIN Sample Voltage Input vided in the block diagram. 4 VOUT Voltage Output During factory calibration, a simple adjustment proce- 5 VCC Power-Supply Voltage dure must be followed. This entire procedure includes setting VIN, toggling ADJ, waiting as VOUT self-adjusts, and waiting for the completion of the EEPROM storage
Block Diagram
cycle (See the timing diagram in Figure 1). At the start of calibration, a voltage must be placed on VIN. This voltage needs to be completely stable before the adjustment procedure begins, and it must remain sta- VCC ble throughout the entire adjustment procedure. The DS4303 DS4303 will start its self-adjust procedure when the RPU ADJ pin is pulled low and held low for at least tADJ, ADJ after which it can be released at any time. Once ADJ ADC VOUT 12-BIT AND has been released, it should not be toggled again for DAC CONTROL the remainder of the adjustment procedure. After the VIN VCC falling edge on ADJ and the wait time, tADJ, the VOUT RPD VREF VCC self-adjust period begins. The length of the VOUT self- EEPROM GND adjust period can be determined using the formula ∆V x tST, where ∆V is | VOUT OLD - VOUT NEW |. V ∆V OUT ∆V OUT OUT ∆V ∆ OUT x tST VOUT x tST VIN tW tW ADJ tADJ tADJ tADJ FIRST PROGRAMMING CYCLE ADDITIONAL PROGRAMMING CYCLES (IF REQUIRED) Figure 1. Timing Diagram
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