Datasheet SY58608U (Microchip)
| Manufacturer | Microchip |
| Description | 2.5V, high-speed, fully differential 1:2 LVDS fanout buffer optimized to provide two identical output copies with less than 20ps of skew and less than 10psPP total jitter |
| Pages / Page | 24 / 1 — SY58608U. 3.2 Gbps Precision, 1:2 LVDS Fanout Buffer with Internal … |
| File Format / Size | PDF / 2.7 Mb |
| Document Language | English |
SY58608U. 3.2 Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and. Fail Safe Input. Features
Model Line for this Datasheet
Text Version of Document
SY58608U 3.2 Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input Features General Description
• Precision 1:2 LVDS Fanout Buffer The SY58608U is a 2.5V, high-speed, fully differential • Guaranteed AC Performance Over Temperature 1:2 LVDS fanout buffer optimized to provide two and Voltage: identical output copies with less than 20 ps of skew and - DC-to > 3.2 Gbps Throughput 130 fsRMS typical additive phase jitter. The SY58608U can process clock signals as fast as 2 GHz or data - <300 ps Propagation Delay (IN-to-Q) patterns up to 3.2 Gbps. - <20 ps Within-Device Skew The differential input includes Microchip’s unique, 3-pin - <100 ps Rise/Fall Times input termination architecture that interfaces to • Fail Safe Input LVPECL, LVDS or CML differential signals, (AC- or - Prevents Outputs From Oscillating When DC-coupled) as small as 100 mV (200 mVPP) without Input Is Invalid any level-shifting or termination resistor networks in the • Ultra-Low Jitter Design signal path. For AC-coupled input interface - 130 fs applications, an integrated voltage reference (V RMS Typical Additive Phase Jitter REF-AC) - High-Speed LVDS Outputs is provided to bias the VT pin. The outputs are 325 mV LVDS, with rise/fall times guaranteed to be less than • 2.5V ±5% Power Supply Operation 100 ps. • Industrial Temperature Range: –40°C to +85°C The SY58608U operates from a 2.5V ±5% supply and • Available In 16-pin (3 mm x 3 mm) QFN Package is guaranteed over the full industrial temperature range (–40°C to +85°C). The SY58608U is part of Microchip’s
Applications
high-speed, Precision Edge® product line. • All SONET Clock And Data Distribution • Fibre Channel Clock And Data Distribution • Gigabit Ethernet Clock And Data Distribution
Package Type
• Backplane Distribution
SY58608U
3x3 QFN-16
Markets
Top View • DataCom • Telecom VCC GND GND VCC • Storage 16 15 14 13 • ATE • Test and Measurement IN 1 12 Q0 VT 2 11 /Q0 VREF-AC 3 10 Q1 /IN 4 9 /Q1 5 6 7 8 VCC GND GND VCC 2018 Microchip Technology Inc. DS20005605A-page 1 Document Outline 1.0 Electrical Characteristics 2.0 Functional Description 2.1 Fail-Safe Input (FSI) 2.2 Input Clock Failure Case 3.0 Timing Diagrams 4.0 Typical Performance Curves 5.0 Additive Phase Noise Plot 6.0 Input Stage 7.0 Input Interface Applications 8.0 Pin Descriptions 9.0 Packaging Information 9.1 Package Marking Information Appendix A: Revision History Product Identification System Worldwide Sales and Service
• Precision 1:2 LVDS Fanout Buffer The SY58608U is a 2.5V, high-speed, fully differential • Guaranteed AC Performance Over Temperature 1:2 LVDS fanout buffer optimized to provide two and Voltage: identical output copies with less than 20 ps of skew and - DC-to > 3.2 Gbps Throughput 130 fsRMS typical additive phase jitter. The SY58608U can process clock signals as fast as 2 GHz or data - <300 ps Propagation Delay (IN-to-Q) patterns up to 3.2 Gbps. - <20 ps Within-Device Skew The differential input includes Microchip’s unique, 3-pin - <100 ps Rise/Fall Times input termination architecture that interfaces to • Fail Safe Input LVPECL, LVDS or CML differential signals, (AC- or - Prevents Outputs From Oscillating When DC-coupled) as small as 100 mV (200 mVPP) without Input Is Invalid any level-shifting or termination resistor networks in the • Ultra-Low Jitter Design signal path. For AC-coupled input interface - 130 fs applications, an integrated voltage reference (V RMS Typical Additive Phase Jitter REF-AC) - High-Speed LVDS Outputs is provided to bias the VT pin. The outputs are 325 mV LVDS, with rise/fall times guaranteed to be less than • 2.5V ±5% Power Supply Operation 100 ps. • Industrial Temperature Range: –40°C to +85°C The SY58608U operates from a 2.5V ±5% supply and • Available In 16-pin (3 mm x 3 mm) QFN Package is guaranteed over the full industrial temperature range (–40°C to +85°C). The SY58608U is part of Microchip’s
Applications
high-speed, Precision Edge® product line. • All SONET Clock And Data Distribution • Fibre Channel Clock And Data Distribution • Gigabit Ethernet Clock And Data Distribution
Package Type
• Backplane Distribution
SY58608U
3x3 QFN-16
Markets
Top View • DataCom • Telecom VCC GND GND VCC • Storage 16 15 14 13 • ATE • Test and Measurement IN 1 12 Q0 VT 2 11 /Q0 VREF-AC 3 10 Q1 /IN 4 9 /Q1 5 6 7 8 VCC GND GND VCC 2018 Microchip Technology Inc. DS20005605A-page 1 Document Outline 1.0 Electrical Characteristics 2.0 Functional Description 2.1 Fail-Safe Input (FSI) 2.2 Input Clock Failure Case 3.0 Timing Diagrams 4.0 Typical Performance Curves 5.0 Additive Phase Noise Plot 6.0 Input Stage 7.0 Input Interface Applications 8.0 Pin Descriptions 9.0 Packaging Information 9.1 Package Marking Information Appendix A: Revision History Product Identification System Worldwide Sales and Service
