Datasheet FL7740 (ON Semiconductor) - 10

FL7740 Primary Side Constant Voltage Regulation
during startup sequence (SS1 + SS2) by using internal FL7740 utilizes auxiliary winding to detect output voltage resistive load at the output of the error amplifier. during secondary side diode conduction time (= TDIS). The In SS1, CCM prevent operation is enabled for the initial true output voltage level without secondary diode forward 2 ms. When output voltage is 0 V, deep CCM could be voltage drop is at the end of secondary diode conduction entered at initial startup and CS could touch OCP level with time. In order to detect the right output voltage, 85% of TDIS startup failure. So, pulse−by−pulse current limit is 0.2 V and at previous switching cycle is sampling time for VEAV switching frequency is 22 kHz during the 2 ms CCM prevent detection at current switching cycle. time. Also, duty is gradually increased for 26 ms for soft startup. Once 5 V pulled−up COMV voltage drops less than
T
4.5 V as V
DIS
EAV is close to VREF, SS1 is ended. Maximum SS1
Error detection
time is limited up to 100 ms.
Amp. V
In SS2, VCOMV drops from 5 V and goes into p−gain
VS REF S/H
steady state in which V
N
EAV is little bit lower than VREF due
AUX VEAV
to the error amplifier input error in p−gain. Once p−gain steady state is settled down in 45 ms, SS2 is finished at min.
COMV
VCOMV range not to make overshoot when transitioning to i−gain after SS2. FL7740 ends SS2 by monitoring VIN
Duty
1.5 ms after VIN.PK detection moment where VCOMV is
VIN.PK Control
generally in the min range.
Figure 15. Primary Side Regulation VIN.PK VIN GATE 1.5 ms VCOMV 5.0 V 4.5 V 26 ms soft start Duty VEAV sampling VS 2 ms CCM prevent VEAV 85% T VREF DIS at previous 45 ms switching SS1 SS2 Startup time by P−gain I−gain TDIS Figure 17. Start up sequnce Figure 16. VEAV Detection Dynamic CV Regulation
Due to the narrow loop bandwidth, PFC controller The sampled VEAV is compared with 3.5 V VREF at the generally does not guarantee good CV regulation at load input of the error amplifier. Several hundreds nF capacitor transient. Especially in secondary side regulation, primary is connected to the output of the error amplifier at COMV side controller does not know the output voltage level and it pin to keep feedback loop slow in PFC control. COMV only monitors the output of feedback signal through voltage controls duty to regulate VEAV same as VREF in the opto−coupler. Therefore, output voltage undershoot is system. severely happened at no to full load transient in the Turn−on time is controlled by both COMV voltage and conventional SSR PFC control. VIN.PK information in line feedforward operation in order to In order to overcome this, FL7740 utilizes the benefit of keep the constant COMV voltage in the wide input voltage PSR with
onsemi
’s proprietary dynamic duty control by range. So, turn−on time is proportional to COMV voltage monitoring the output voltage. For example, when VEAV is and inversely proportional to VIN.PK. less than VUVD.EN (Under Voltage Dynamic Enable
Startup
threshold), duty is quickly increased not to allow undershoot After plug−in, external VDD capacitor is quickly charged anymore. Once VEAV rises higher than VUVD.DIS (Under by internal HV biasing supply. Even after VDD is higher Voltage Dynamic Disable threshold), duty quickly drops than 16 V V and follows COMV voltage. During the VEAV hiccup DD−ON, internal HV biasing is still enabled for 500 ms, so HV biasing can relieve VDD capacitor operation, COMV voltage slowly increases and dynamic discharging until auxiliary winding builds up VDD voltage. operation is terminated when COMV voltage is close to In order to speed up large output capacitor charging steady state level. without overshoot, FL7740 starts with proportional gain
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