Datasheet HEF4013B (Nexperia) - 3

Nexperia HEF4013B Dual D-type flip-flop 6. Pinning information 6.1. Pinning T package SOT108-1 (SO14)
1Q 1 14 VDD
TT package SOT402-1 (TSSOP14)
1Q 2 13 2Q 1CP 3 12 2Q 1Q 1 14 VDD 1Q 2 13 2Q 1CD 4 11 2CP 1CP 3 12 2Q 1D 5 10 2CD 1CD 4 11 2CP 1D 5 10 2CD 1SD 6 9 2D 1SD 6 9 2D VSS 7 8 2SD VSS 7 8 2SD aaa-039618 aaa-039634
6.2. Pin description Table 2. Pin description Symbol Pin Description
1Q, 2Q 1, 13 true output 1Q, 2Q 2, 12 complement output 1CP, 2CP 3, 11 clock input (LOW to HIGH edge-triggered) 1CD, 2CD 4, 10 asynchronous clear-direct input (active HIGH) 1D, 2D 5, 9 data input 1SD, 2SD 6, 8 asynchronous set-direct input (active HIGH) VSS 7 ground (0 V) VDD 14 supply voltage
7. Functional description Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition.
Control Input Output nSD nCD nCP nD nQ nQ
H L X X H L L H X X L H H H X X H H L L ↑ L L H L L ↑ H H L HEF4013B All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2024. Al rights reserved
Product data sheet Rev. 12 — 24 July 2024 3 / 14
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1. Pinning 6.2. Pin description 7. Functional description 8. Limiting values 9. Recommended operating conditions 10. Static characteristics 11. Dynamic characteristics 11.1. Waveforms and test circuit 12. Application information 13. Package outline 14. Abbreviations 15. Revision history 16. Legal information Contents