Datasheet ACT 1 (Actel) - 9

A C T ™ 1 S e r i e s F P G A s F u n c t i o n a l T i m i n g T e s t s
logic modules are distributed along two sides of the device, as AC timing for logic module internal delays is determined inverting or non-inverting buffers. The modules are after place and route. The DirectTime Analyzer utility connected through programmed antifuses with typical displays actual timing parameters for circuit delays. ACT 1 capacitive loading. devices are AC tested to a “binning” circuit specification. Propagation delay [tPD = (tPLH + tPHL)/2] is tested to the The circuit consists of one input buffer + n logic modules + following AC test specifications. one output buffer (n = 16 for A1010B; n = 28 for A1020B). The
O u t p u t B u f f e r P e r f o r m a n c e D e r a t i n g ( 5 V ) Sink Source
12 –4 10 –6 8 (mA) (mA) –8 I OL I OH 6 –10 4 –12 0.2 0.3 0.4 0.5 0.6 4.0 3.6 3.2 2.8 2.4 2.0 VOL (Volts) VOH (Volts) Military, worst-case values at 125°C, 4.5 V. Commercial, worst-case values at 70°C, 4.75 V.
Note:
The above curves are based on characterizations of sample devices and are not completely tested on all devices.
O u t p u t B u f f e r P e r f o r m a n c e D e r a t i n g ( 3 . 3 V ) Sink Source
12 –4 10 –6 8 (mA) (mA) –8 I OL I OH 6 –10 4 –12 0.0 0.1 0.2 0.3 0.4 0 0.5 1.0 1.5 2.0 2.5 VOL (Volts) VOH (Volts) Commercial, worst-case values at 70°C, 4.75 V.
Note:
The above curves are based on characterizations of sample devices and are not completely tested on all devices.
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Document Outline ACT™ 1 Series FPGAs Features Description Product Family Profile The Designer and Designer Advantage™ Systems ACT 1 Device Structure The ACT 1 Logic Module I/O Buffers Device Organization Probe Pin ACT 1 Array Performance Temperature and Voltage Effects Logic Module Size Ordering Information Product Plan Device Resources Pin Description Absolute Maximum Ratings1 Free air temperature range Recommended Operating Conditions Electrical Specifications (5V) Electrical Specifications (3.3V) Package Thermal Characteristics General Power Equation Static Power Component Active Power Component Equivalent Capacitance CEQ Values for Actel FPGAs Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Functional Timing Tests Output Buffer Performance Derating (5V) Output Buffer Performance Derating (3.3V) ACT 1 Timing Module* Predictable Performance: Tight Delay Distributions... Timing Characteristics Critical Nets and Typical Nets Long Tracks Timing Derating Timing Derating Factor (Temperature and Voltage) Timing Derating Factor for Designs at Typical Temp... Temperature and Voltage Derating Factors (normaliz... Temperature and Voltage Derating Factors (normaliz... Junction Temperature and Voltage Derating Curves (... Parameter Measurement Output Buffer Delays AC Test Loads Input Buffer Delays Module Delays Sequential Timing Characteristics Flip-Flops and Latches ACT 1 Timing Characteristics (Worst-Case Commercial Conditions, VCC = 4.75 V,T... ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Package Pin Assignments 44-Pin PLCC 68-Pin PLCC Package Pin Assignments (continued) 84-Pin PLCC Package Pin Assignments (continued) 100-Pin PQFP Package Pin Assignments (continued) 80-Pin VQFP Package Pin Assignments (continued) 84-Pin CPGA Package Pin Assignments (continued) 84-Pin CQFP