Preliminary Datasheet EPC2102 (Efficient Power Conversion) - 2
| Manufacturer | Efficient Power Conversion |
| Description | Enhancement-Mode GaN Power Transistor Half Bridge |
| Pages / Page | 10 / 2 — EPC2102 – Enhancement-Mode GaN Power Transistor Half Bridge. Preliminary … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
EPC2102 – Enhancement-Mode GaN Power Transistor Half Bridge. Preliminary Specification Sheet. STATIC CHARACTERISTICS
Model Line for this Datasheet
EPC2102
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EPC2102 – Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet STATIC CHARACTERISTICS Parameter Conditions Q1 Control FET Q2 Sync FET
Q1: V Maximum Drain – Source Voltage (BV GS = 0 V, ID = 430 µA DSS) 60 V Q2: VGS = 0 V, ID = 430 µA Maximum Drain – Source Leakage VDS = 48 V, VGS = 0 V 360 µA 360 µA Maximum RDS(on) VGS = 5 V, ID = 20 A 4.4 mΩ 4.4 mΩ Typical RDS(on) VGS = 5 V, ID = 20 A 3.2 mΩ 3.2 mΩ Q1: I Gate – Source Threshold Voltage D = 7 mA, VDS = VGS 0.8 V < VGS(TH) < 2.5 V Q2: ID = 7 mA, VDS = VGS Gate – Source Maximum Positive Leakage VGS = 5 V 7 mA 7 mA Gate – Source Maximum Negative Leakage VGS = -4 V -360 µA -360 µA TJ = 25 °C unless otherwise stated
DYNAMIC CHARACTERISTICS Typical Value Parameter Conditions Q1 Control FET Q2 Sync FET Unit
C 0.83 0.83 ISS (Input Capacitance) C 0.51 0.71 OSS (Output Capacitance) V nF DS = 30 V, VGS = 0 V CRSS (Reverse Transfer Capacitance) 0.014 0.014 QG (Total Gate Charge) VDS = 30 V, ID = 20 A, VGS = 5 V 6.8 6.8 Q 2.3 2.3 GS (Gate to Source Charge) Q 1.4 1.4 GD (Gate to Drain Charge) VDS = 30 V, ID = 20 A nC QG(TH) (Gate Charge at Threshold) 1.8 1.8 QOSS (Output Charge) VDS = 30 V, VGS = 0 V 23 31 QRR (Source-Drain Recovery Charge) 0 0 TJ = 25 °C unless otherwise stated Subject to Change without Notice www.epc-co.com COPYRIGHT 2015 Page 2
Q1: V Maximum Drain – Source Voltage (BV GS = 0 V, ID = 430 µA DSS) 60 V Q2: VGS = 0 V, ID = 430 µA Maximum Drain – Source Leakage VDS = 48 V, VGS = 0 V 360 µA 360 µA Maximum RDS(on) VGS = 5 V, ID = 20 A 4.4 mΩ 4.4 mΩ Typical RDS(on) VGS = 5 V, ID = 20 A 3.2 mΩ 3.2 mΩ Q1: I Gate – Source Threshold Voltage D = 7 mA, VDS = VGS 0.8 V < VGS(TH) < 2.5 V Q2: ID = 7 mA, VDS = VGS Gate – Source Maximum Positive Leakage VGS = 5 V 7 mA 7 mA Gate – Source Maximum Negative Leakage VGS = -4 V -360 µA -360 µA TJ = 25 °C unless otherwise stated
DYNAMIC CHARACTERISTICS Typical Value Parameter Conditions Q1 Control FET Q2 Sync FET Unit
C 0.83 0.83 ISS (Input Capacitance) C 0.51 0.71 OSS (Output Capacitance) V nF DS = 30 V, VGS = 0 V CRSS (Reverse Transfer Capacitance) 0.014 0.014 QG (Total Gate Charge) VDS = 30 V, ID = 20 A, VGS = 5 V 6.8 6.8 Q 2.3 2.3 GS (Gate to Source Charge) Q 1.4 1.4 GD (Gate to Drain Charge) VDS = 30 V, ID = 20 A nC QG(TH) (Gate Charge at Threshold) 1.8 1.8 QOSS (Output Charge) VDS = 30 V, VGS = 0 V 23 31 QRR (Source-Drain Recovery Charge) 0 0 TJ = 25 °C unless otherwise stated Subject to Change without Notice www.epc-co.com COPYRIGHT 2015 Page 2
