Preliminary Datasheet SAM E70 - 9

Table 3-1. Signal Description List (Continued) Active Voltage Signal Name Function Type Level Reference Comments PIO Controller - Parallel Capture Mode
PIODC0–PIODC7 Parallel Capture Mode Data Input – PIODCCLK Parallel Capture Mode Clock Input – VDDIO – PIODCEN1–PIODCEN2 Parallel Capture Mode Enable Input –
External Bus Interface
D[15:0] Data Bus I/O – – – A[23:0] Address Bus Output – – – NWAIT External Wait Signal Input Low – –
Static Memory Controller - SMC
NCS0–NCS3 Chip Select Lines Output Low – – NRD Read Signal Output Low – – NWE Write Enable Output Low – – NWR0–NWR1 Write Signal Output Low – – NBS0–NBS1 Byte Mask Signal Output Low – Used also for SDRAMC
NAND Flash Logic
NANDOE NAND Flash Output Enable Output Low – – NANDWE NAND Flash Write Enable Output Low – –
SDR-SDRAM Controller Logic
SDCK SDRAM Clock Output – – – SDCKE SDRAM Clock Enable Output – – – SDCS SDRAM Controller Chip Select Output – – – BA0–BA1 Bank Select Output – – – SDWE SDRAM Write Enable Output – – – RAS–CAS Row and Column Signal Output – – – SDA10 SDRAM Address 10 Line Output – – –
High Speed Multimedia Card Interface - HSMCI
MCCK Multimedia Card Clock I/O – – – Multimedia Card Slot A MCCDA I/O – – – Command MCDA0–MCDA3 Multimedia Card Slot A Data I/O – – – SAM E70 [PRELIMINARY DATASHEET] 9 Atmel-11297B-ATARM-SAM E70-Preliminary Datasheet_24-Feb-15 Document Outline Description Features 1. Configuration Summary 2. Block Diagram 3. Signal Description 4. Package and Pinout 4.1 144-lead Packages 4.1.1 144-pin LQFP Package Outline 4.1.2 144-ball LFBGA Package Outline 4.2 144-lead Package Pinout 4.3 100-lead Packages 4.3.1 100-pin LQFP Package Outline 4.3.2 100-ball TFBGA Package Outline 4.4 100-lead Package Pinout 4.5 64-lead Packages 4.5.1 64-pin LQFP Package Outline 4.6 64-lead Package Pinout 5. Power Considerations 5.1 Power Supplies 5.2 Power Constraints 5.2.1 Power-up 5.2.2 Power-down 5.3 Voltage Regulator 5.4 Backup SRAM Power Switch 5.5 Typical Powering Schematics 5.6 Active Mode 5.7 Low-power Modes 5.7.1 Backup Mode 5.7.2 Wait Mode 5.7.3 Sleep Mode 5.7.4 Low-Power Mode Summary Table 5.8 Wake-up Sources 5.9 Fast Startup 6. Input/Output Lines 6.1 General-Purpose I/O Lines 6.2 System I/O Lines 6.2.1 Serial Wire Debug Port (SW-DP) Pins 6.2.2 Embedded Trace Module (ETM) Pins 6.3 TST Pin 6.4 NRST Pin 6.5 ERASE Pin 7. Interconnect 8. Product Mapping 9. Memories 9.1 Embedded Memories 9.1.1 Internal SRAM 9.1.2 Tightly Coupled Memory (TCM) Interface 9.1.3 Internal ROM 9.1.4 Backup SRAM 9.1.5 Flash Memories 9.1.5.1 Embedded Flash Overview 9.1.5.2 Enhanced Embedded Flash Controller 9.1.5.3 Flash Speed 9.1.5.4 Lock Regions 9.1.5.5 Security Bit Feature 9.1.5.6 Calibration Bits 9.1.5.7 Unique Identifier 9.1.5.8 User Signature 9.1.5.9 Fast Flash Programming Interface 9.1.5.10 SAM-BA Boot 9.1.5.11 General-purpose NVM (GPNVM) Bits 9.1.6 Boot Strategies 9.2 External Memories 10. Event System 10.1 Embedded Characteristics 10.2 Real-time Event Mapping 11. System Controller 11.1 System Controller and Peripherals Mapping 11.2 Power-on-Reset, Brownout and Supply Monitor 11.2.1 Power-on-Reset 11.2.2 Brownout Detector on VDDCORE 11.2.3 Supply Monitor on VDDIO 11.3 Reset Controller 12. Peripherals 12.1 Peripheral Identifiers 12.2 Peripheral Signal Multiplexing on I/O Lines 13. ARM Cortex-M7 Processor 13.1 Reference Documents 13.2 Description 13.2.1 System-Level Interface 13.2.2 Integrated Configurable Debug 13.3 Embedded Characteristics 13.4 Block Diagram 13.5 Programmer’s Model 13.5.1 Processor Modes and Privilege Levels for Software Execution 13.5.2 Stacks 13.5.2.1 Core Registers 13.5.3 General-purpose Registers 13.5.4 Stack Pointer 13.5.5 Link Register 13.5.6 Program Counter 13.5.6.1 Program Status Register 13.5.6.2 Application Program Status Register 13.5.6.3 Interrupt Program Status Register 13.5.6.4 Execution Program Status Register 13.5.6.5 Exception Mask Registers 13.5.6.6 Priority Mask Register 13.5.6.7 Fault Mask Register 13.5.6.8 Base Priority Mask Register 13.5.6.9 Control Register 13.5.6.10 Exceptions and Interrupts 13.5.6.11 Data Types 13.5.6.12 Cortex Microcontroller Software Interface Standard (CMSIS) 13.6 Cortex-M7 Configuration 14. Debug and Test Features 14.1 Description 14.2 Embedded Characteristics 14.3 Debug and Test Block Diagram 14.4 Debug and Test Pin Description 14.5 Application Examples 14.5.1 Debug Environment 14.5.2 Test Environment 14.6 Functional Description 14.6.1 Test Pin 14.6.2 NRST Pin 14.6.3 ERASE Pin 14.6.4 Debug Architecture 14.6.5 Serial Wire Debug Port (SW-DP) Pins 14.6.6 Embedded Trace Module (ETM) Pins 14.6.7 Flash Patch Breakpoint (FPB) 14.6.8 Data Watchpoint and Trace (DWT) 14.6.9 Instrumentation Trace Macrocell (ITM) 14.6.9.1 How to Configure the ITM 14.6.9.2 Asynchronous Mode 14.6.9.3 How to Configure the TPIU 14.6.10 IEEE1149.1 JTAG Boundary Scan 14.6.10.1 JTAG Boundary Scan Register 14.6.11 ID Code Register 15. SAM-BA Boot Program 15.1 Description 15.2 Embedded Characteristics 15.3 Hardware and Software Constraints 15.4 Flow Diagram 15.5 Device Initialization 15.6 SAM-BA Monitor 15.6.1 UART0 Serial Port 15.6.2 Xmodem Protocol 15.6.3 USB Device Port 15.6.3.1 Enumeration Process 15.6.3.2 Communication Endpoints 15.6.4 In Application Programming (IAP) Feature 16. Fast Flash Programming Interface (FFPI) 16.1 Description 16.2 Embedded Characteristics 16.3 Parallel Fast Flash Programming 16.3.1 Device Configuration 16.3.2 Signal Names 16.3.3 Entering Programming Mode 16.3.4 Programmer Handshaking 16.3.4.1 Write Handshaking 16.3.4.2 Read Handshaking 16.3.5 Device Operations 16.3.5.1 Flash Read Command 16.3.5.2 Flash Write Command 16.3.5.3 Flash Full Erase Command 16.3.5.4 Flash Lock Commands 16.3.5.5 Flash General-purpose NVM Commands 16.3.5.6 Flash Security Bit Command 16.3.5.7 Memory Write Command 16.3.5.8 Get Version Command 17. Bus Matrix (MATRIX) 17.1 Description 17.2 Embedded Characteristics 17.2.1 Matrix Masters 17.2.2 Matrix Slaves 17.2.3 Master to Slave Access 17.3 Memory Mapping 17.4 Special Bus Granting Mechanism 17.5 No Default Master 17.6 Last Access Master 17.7 Fixed Default Master 17.8 Arbitration 17.8.1 Arbitration Scheduling 17.8.1.1 Undefined Length Burst Arbitration 17.8.1.2 Slot Cycle Limit Arbitration 17.8.2 Arbitration Priority Scheme 17.8.2.1 Fixed Priority Arbitration 17.8.2.2 Round-Robin Arbitration 17.9 System I/O Configuration 17.10 SMC NAND Flash Chip Select Configuration 17.11 Register Write Protection 17.12 Bus Matrix (MATRIX) User Interface 17.12.1 Bus Matrix Master Configuration Registers 17.12.2 Bus Matrix Slave Configuration Registers 17.12.3 Bus Matrix Priority Registers A For Slaves 17.12.4 Bus Matrix Priority Registers B For Slaves 17.12.5 Bus Matrix Master Remap Control Register 17.12.6 CAN0 Configuration Register 17.12.7 System I/O and CAN1 Configuration Register 17.12.8 SMC NAND Flash Chip Select Configuration Register 17.12.9 Write Protection Mode Register 17.12.10 Write Protection Status Register 18. USB Transmitter Macrocell Interface (UTMI) 18.1 Description 18.2 Embedded Characteristics 18.3 USB Transmitter Macrocell Interface (UTMI) User Interface 18.3.1 OHCI Interrupt Configuration Register 18.3.2 UTMI Clock Trimming Register 19. Chip Identifier (CHIPID) 19.1 Description 19.2 Embedded Characteristics 19.3 Chip Identifier (CHIPID) User Interface 19.3.1 Chip ID Register 19.3.2 Chip ID Extension Register 20. Enhanced Embedded Flash Controller (EEFC) 20.1 Description 20.2 Embedded Characteristics 20.3 Product Dependencies 20.3.1 Power Management 20.3.2 Interrupt Sources 20.4 Functional Description 20.4.1 Embedded Flash Organization 20.4.2 Read Operations 20.4.2.1 Code Read Optimization 20.4.2.2 Code Loop Optimization 20.4.2.3 Data Read Optimization 20.4.3 Flash Commands 20.4.3.1 Get Flash Descriptor Command 20.4.3.2 Write Commands Full Page Programming Partial Page Programming Optimized Partial Page Programming Programming Bytes 20.4.3.3 Erase Commands 20.4.3.4 Lock Bit Protection 20.4.3.5 GPNVM Bit 20.4.3.6 Calibration Bit 20.4.3.7 Security Bit Protection 20.4.3.8 Unique Identifier 20.4.3.9 User Signature 20.4.3.10 ECC Errors and Corrections 20.4.4 Register Write Protection 20.5 Enhanced Embedded Flash Controller (EEFC) User Interface 20.5.1 EEFC Flash Mode Register 20.5.2 EEFC Flash Command Register 20.5.3 EEFC Flash Status Register 20.5.4 EEFC Flash Result Register 20.5.5 EEFC Write Protection Mode Register 21. Supply Controller (SUPC) 21.1 Description 21.2 Embedded Characteristics 21.3 Block Diagram 21.4 Functional Description 21.4.1 Overview 21.4.2 Slow Clock Generator 21.4.3 Core Voltage Regulator Control/Backup Low-power Mode 21.4.4 Using Backup Batteries/Backup Supply 21.4.5 Supply Monitor 21.4.6 Backup Power Supply Reset 21.4.6.1 Raising the Backup Power Supply 21.4.7 Core Reset 21.4.7.1 Supply Monitor Reset 21.4.7.2 Brownout Detector Reset 21.4.8 Controlling the SRAM Power Supply 21.4.9 Wake-up Sources 21.4.9.1 Wake-up Inputs 21.4.9.2 Low-power Tamper Detection and Anti-Tampering 21.4.9.3 Clock Alarms 21.4.9.4 Supply Monitor Detection 21.4.10 Register Write Protection 21.4.11 Register Bits in Backup Domain (VDDIO) 21.5 Supply Controller (SUPC) User Interface 21.5.1 System Controller (SYSC) User Interface 21.5.2 Supply Controller (SUPC) User Interface 21.5.3 Supply Controller Control Register 21.5.4 Supply Controller Supply Monitor Mode Register 21.5.5 Supply Controller Mode Register 21.5.6 Supply Controller Wake-up Mode Register 21.5.7 Supply Controller Wake-up Inputs Register 21.5.8 Supply Controller Status Register 21.5.9 System Controller Write Protection Mode Register 22. Watchdog Timer (WDT) 22.1 Description 22.2 Embedded Characteristics 22.3 Block Diagram 22.4 Functional Description 22.5 Watchdog Timer (WDT) User Interface 22.5.1 Watchdog Timer Control Register 22.5.2 Watchdog Timer Mode Register 22.5.3 Watchdog Timer Status Register 23. Reinforced Safety Watchdog Timer (RSWDT) 23.1 Description 23.2 Embedded Characteristics 23.3 Block Diagram 23.4 Functional Description 23.5 Reinforced Safety Watchdog Timer (RSWDT) User Interface 23.5.1 Reinforced Safety Watchdog Timer Control Register 23.5.2 Reinforced Safety Watchdog Timer Mode Register 23.5.3 Reinforced Safety Watchdog Timer Status Register 24. Reset Controller (RSTC) 24.1 Description 24.2 Embedded Characteristics 24.3 Block Diagram 24.4 Functional Description 24.4.1 Reset Controller Overview 24.4.2 NRST Manager 24.4.2.1 NRST Signal or Interrupt 24.4.2.2 NRST External Reset Control 24.4.3 Reset States 24.4.3.1 General Reset 24.4.3.2 Backup Reset 24.4.3.3 Watchdog Reset 24.4.3.4 Software Reset 24.4.3.5 User Reset 24.4.4 Reset State Priorities 24.5 Reset Controller (RSTC) User Interface 24.5.1 Reset Controller Control Register 24.5.2 Reset Controller Status Register 24.5.3 Reset Controller Mode Register 25. Real-time Clock (RTC) 25.1 Description 25.2 Embedded Characteristics 25.3 Block Diagram 25.4 Product Dependencies 25.4.1 Power Management 25.4.2 Interrupt 25.5 Functional Description 25.5.1 Reference Clock 25.5.2 Timing 25.5.3 Alarm 25.5.4 Error Checking when Programming 25.5.5 RTC Internal Free Running Counter Error Checking 25.5.6 Updating Time/Calendar 25.5.7 RTC Accurate Clock Calibration 25.5.8 Waveform Generation 25.6 Real-time Clock (RTC) User Interface 25.6.1 RTC Control Register 25.6.2 RTC Mode Register 25.6.3 RTC Time Register 25.6.4 RTC Calendar Register 25.6.5 RTC Time Alarm Register 25.6.6 RTC Calendar Alarm Register 25.6.7 RTC Status Register 25.6.8 RTC Status Clear Command Register 25.6.9 RTC Interrupt Enable Register 25.6.10 RTC Interrupt Disable Register 25.6.11 RTC Interrupt Mask Register 25.6.12 RTC Valid Entry Register 26. Real-time Timer (RTT) 26.1 Description 26.2 Embedded Characteristics 26.3 Block Diagram 26.4 Functional Description 26.5 Real-time Timer (RTT) User Interface 26.5.1 Real-time Timer Mode Register 26.5.2 Real-time Timer Alarm Register 26.5.3 Real-time Timer Value Register 26.5.4 Real-time Timer Status Register 27. General Purpose Backup Registers (GPBR) 27.1 Description 27.2 Embedded Characteristics 27.3 General Purpose Backup Registers (GPBR) User Interface 27.3.1 General Purpose Backup Register x 28. Clock Generator 28.1 Description 28.2 Embedded Characteristics 28.3 Block Diagram 28.4 Slow Clock 28.4.1 Slow Clock RC Oscillator 28.4.2 Slow Clock Crystal Oscillator 28.5 Main Clock 28.5.1 Fast RC Oscillator 28.5.2 Fast RC Oscillator Clock Frequency Adjustment 28.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator 28.5.4 Main Clock Oscillator Selection 28.5.5 Bypassing the Main Crystal Oscillator 28.5.6 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator 28.5.7 Software Sequence to Detect the Presence of Fast Crystal 28.5.8 Main Clock Frequency Counter 28.6 Divider and PLL Block 28.6.1 Divider and Phase Lock Loop Programming 28.7 UTMI Phase Lock Loop Programming 29. Power Management Controller (PMC) 29.1 Description 29.2 Embedded Characteristics 29.3 Block Diagram 29.4 Master Clock Controller 29.5 Processor Clock Controller 29.6 SysTick Clock 29.7 USB Clock Controller 29.8 Peripheral Clock Controller 29.9 Asynchronous Partial Wake-up 29.9.1 Description 29.9.2 Asynchronous Partial Wake-up in Wait Mode (SleepWalking) 29.9.2.1 Configuration Procedure 29.9.3 Asynchronous Partial Wake-Up in Active Mode 29.9.3.1 Configuration Procedure 29.10 Free-Running Processor Clock 29.11 Programmable Clock Output Controller 29.12 Core and Bus Independent Clocks for Peripherals 29.13 Fast Startup 29.14 Startup from Embedded Flash 29.15 Main Clock Failure Detection 29.16 Slow Crystal Clock Frequency Monitor 29.17 Programming Sequence 29.18 Clock Switching Details 29.18.1 Master Clock Switching Timings 29.18.2 Clock Switching Waveforms 29.19 Register Write Protection 29.20 Power Management Controller (PMC) User Interface 29.20.1 PMC System Clock Enable Register 29.20.2 PMC System Clock Disable Register 29.20.3 PMC System Clock Status Register 29.20.4 PMC Peripheral Clock Enable Register 0 29.20.5 PMC Peripheral Clock Disable Register 0 29.20.6 PMC Peripheral Clock Status Register 0 29.20.7 PMC UTMI Clock Configuration Register 29.20.8 PMC Clock Generator Main Oscillator Register 29.20.9 PMC Clock Generator Main Clock Frequency Register 29.20.10 PMC Clock Generator PLLA Register 29.20.11 PMC Master Clock Register 29.20.12 PMC USB Clock Register 29.20.13 PMC Programmable Clock Register 29.20.14 PMC Interrupt Enable Register 29.20.15 PMC Interrupt Disable Register 29.20.16 PMC Status Register 29.20.17 PMC Interrupt Mask Register 29.20.18 PMC Fast Startup Mode Register 29.20.19 PMC Fast Startup Polarity Register 29.20.20 PMC Fault Output Clear Register 29.20.21 PMC Write Protection Mode Register 29.20.22 PMC Write Protection Status Register 29.20.23 PMC Peripheral Clock Enable Register 1 29.20.24 PMC Peripheral Clock Disable Register 1 29.20.25 PMC Peripheral Clock Status Register 1 29.20.26 PMC Peripheral Control Register 29.20.27 PMC Oscillator Calibration Register 29.20.28 PMC SleepWalking Enable Register 0 29.20.29 PMC SleepWalking Enable Register 1 29.20.30 PMC SleepWalking Disable Register 0 29.20.31 PMC SleepWalking Disable Register 1 29.20.32 PMC SleepWalking Status Register 0 29.20.33 PMC SleepWalking Status Register 1 29.20.34 PMC SleepWalking Activity Status Register 0 29.20.35 PMC SleepWalking Activity Status Register 1 29.20.36 PMC SleepWalking Activity In Progress Register 30. Parallel Input/Output Controller (PIO) 30.1 Description 30.2 Embedded Characteristics 30.3 Block Diagram 30.4 Product Dependencies 30.4.1 Pin Multiplexing 30.4.2 External Interrupt Lines 30.4.3 Power Management 30.4.4 Interrupt Sources 30.5 Functional Description 30.5.1 Pull-up and Pull-down Resistor Control 30.5.2 I/O Line or Peripheral Function Selection 30.5.3 Peripheral A or B or C or D Selection 30.5.4 Output Control 30.5.5 Synchronous Data Output 30.5.6 Multi-Drive Control (Open Drain) 30.5.7 Output Line Timings 30.5.8 Inputs 30.5.9 Input Glitch and Debouncing Filters 30.5.10 Input Edge/Level Interrupt 30.5.11 I/O Lines Lock 30.5.12 Programmable I/O Drive 30.5.13 Programmable Schmitt Trigger 30.5.14 Keypad Controller 30.5.14.1 Overview 30.5.14.2 Functional Description 30.5.14.3 Interrupt Generation 30.5.14.4 Programming the Keypad Controller Debouncing Register 30.5.14.5 Ghost Key Issue 30.5.15 Parallel Capture Mode 30.5.15.1 Overview 30.5.15.2 Functional Description 30.5.15.3 Restrictions 30.5.15.4 Programming Sequence 30.5.16 I/O Lines Programming Example 30.5.17 Register Write Protection 30.6 Parallel Input/Output Controller (PIO) User Interface 30.6.1 PIO Enable Register 30.6.2 PIO Disable Register 30.6.3 PIO Status Register 30.6.4 PIO Output Enable Register 30.6.5 PIO Output Disable Register 30.6.6 PIO Output Status Register 30.6.7 PIO Input Filter Enable Register 30.6.8 PIO Input Filter Disable Register 30.6.9 PIO Input Filter Status Register 30.6.10 PIO Set Output Data Register 30.6.11 PIO Clear Output Data Register 30.6.12 PIO Output Data Status Register 30.6.13 PIO Pin Data Status Register 30.6.14 PIO Interrupt Enable Register 30.6.15 PIO Interrupt Disable Register 30.6.16 PIO Interrupt Mask Register 30.6.17 PIO Interrupt Status Register 30.6.18 PIO Multi-driver Enable Register 30.6.19 PIO Multi-driver Disable Register 30.6.20 PIO Multi-driver Status Register 30.6.21 PIO Pull-Up Disable Register 30.6.22 PIO Pull-Up Enable Register 30.6.23 PIO Pull-Up Status Register 30.6.24 PIO Peripheral ABCD Select Register 1 30.6.25 PIO Peripheral ABCD Select Register 2 30.6.26 PIO Input Filter Slow Clock Disable Register 30.6.27 PIO Input Filter Slow Clock Enable Register 30.6.28 PIO Input Filter Slow Clock Status Register 30.6.29 PIO Slow Clock Divider Debouncing Register 30.6.30 PIO Pad Pull-Down Disable Register 30.6.31 PIO Pad Pull-Down Enable Register 30.6.32 PIO Pad Pull-Down Status Register 30.6.33 PIO Output Write Enable Register 30.6.34 PIO Output Write Disable Register 30.6.35 PIO Output Write Status Register 30.6.36 PIO Additional Interrupt Modes Enable Register 30.6.37 PIO Additional Interrupt Modes Disable Register 30.6.38 PIO Additional Interrupt Modes Mask Register 30.6.39 PIO Edge Select Register 30.6.40 PIO Level Select Register 30.6.41 PIO Edge/Level Status Register 30.6.42 PIO Falling Edge/Low-Level Select Register 30.6.43 PIO Rising Edge/High-Level Select Register 30.6.44 PIO Fall/Rise - Low/High Status Register 30.6.45 PIO Lock Status Register 30.6.46 PIO Write Protection Mode Register 30.6.47 PIO Write Protection Status Register 30.6.48 PIO Schmitt Trigger Register 30.6.49 PIO I/O Drive Register 30.6.50 PIO Keypad Controller Enable Register 30.6.51 PIO Keypad Controller Row Column Register 30.6.52 PIO Keypad Controller Debouncing Register 30.6.53 PIO Keypad Controller Interrupt Enable Register 30.6.54 PIO Keypad Controller Interrupt Disable Register 30.6.55 PIO Keypad Controller Interrupt Mask Register 30.6.56 PIO Keypad Controller Status Register 30.6.57 PIO Keypad Controller Key Press Register 30.6.58 PIO Keypad Controller Key Release Register 30.6.59 PIO Parallel Capture Mode Register 30.6.60 PIO Parallel Capture Interrupt Enable Register 30.6.61 PIO Parallel Capture Interrupt Disable Register 30.6.62 PIO Parallel Capture Interrupt Mask Register 30.6.63 PIO Parallel Capture Interrupt Status Register 30.6.64 PIO Parallel Capture Reception Holding Register 31. External Bus Interface (EBI) 31.1 Description 31.2 Embedded Characteristics 31.3 EBI Block Diagram 31.4 I/O Lines Description 31.5 Application Example 31.5.1 Hardware Interface 31.5.2 Product Dependencies 31.5.2.1 I/O Lines 31.5.3 Functional Description 31.5.3.1 Bus Multiplexing 31.5.3.2 Static Memory Controller 31.5.3.3 SDRAM Controller 31.5.3.4 NAND Flash Support 31.5.4 Implementation Examples 31.5.4.1 16-bit SDRAM on NCS1 32. SDRAM Controller (SDRAMC) 32.1 Description 32.2 Embedded Characteristics 32.3 Signal Description 32.4 Software Interface/SDRAM Organization, Address Mapping 32.4.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width 32.5 Product Dependencies 32.5.1 SDRAM Device Initialization 32.5.2 I/O Lines 32.5.3 Power Management 32.5.4 Interrupt Sources 32.6 Functional Description 32.6.1 SDRAM Controller Write Cycle 32.6.2 SDRAM Controller Read Cycle 32.6.3 Border Management 32.6.4 SDRAM Controller Refresh Cycles 32.6.5 Power Management 32.6.5.1 Self-refresh Mode 32.6.5.2 Low-power Mode 32.6.5.3 Deep Power-down Mode 32.6.6 Scrambling/Unscrambling Function 32.7 SDRAM Controller (SDRAMC) User Interface 32.7.1 SDRAMC Mode Register 32.7.2 SDRAMC Refresh Timer Register 32.7.3 SDRAMC Configuration Register 32.7.4 SDRAMC Low Power Register 32.7.5 SDRAMC Interrupt Enable Register 32.7.6 SDRAMC Interrupt Disable Register 32.7.7 SDRAMC Interrupt Mask Register 32.7.8 SDRAMC Interrupt Status Register 32.7.9 SDRAMC Memory Device Register 32.7.10 SDRAMC Configuration Register 1 32.7.11 SDRAMC OCMS Register 32.7.12 SDRAMC OCMS KEY1 Register 32.7.13 SDRAMC OCMS KEY2 Register 33. Static Memory Controller (SMC) 33.1 Description 33.2 Embedded Characteristics 33.3 I/O Lines Description 33.4 Product Dependencies 33.4.1 I/O Lines 33.4.2 Power Management 33.5 Multiplexed Signals 33.6 External Memory Mapping 33.7 Connection to External Devices 33.7.1 Data Bus Width 33.7.2 Byte Write or Byte Select Access 33.7.2.1 Byte Write Access 33.7.2.2 Byte Select Access 33.7.2.3 Signal Multiplexing 33.7.3 NAND Flash Support 33.8 Application Example 33.8.1 Implementation Examples 33.8.1.1 8-bit NAND Flash Hardware Configuration Software Configuration 33.8.1.2 NOR Flash Hardware Configuration Software Configuration 33.9 Standard Read and Write Protocols 33.9.1 Read Waveforms 33.9.1.1 NRD Waveform 33.9.1.2 NCS Waveform 33.9.1.3 Read Cycle 33.9.1.4 Null Delay Setup and Hold 33.9.1.5 Null Pulse 33.9.2 Read Mode 33.9.2.1 Read is Controlled by NRD (READ_MODE = 1): 33.9.2.2 Read is Controlled by NCS (READ_MODE = 0) 33.9.3 Write Waveforms 33.9.3.1 NWE Waveforms 33.9.3.2 NCS Waveforms 33.9.3.3 Write Cycle 33.9.3.4 Null Delay Setup and Hold 33.9.3.5 Null Pulse 33.9.4 Write Mode 33.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1): 33.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0) 33.9.5 Register Write Protection 33.9.6 Coding Timing Parameters 33.9.7 Reset Values of Timing Parameters 33.9.8 Usage Restriction 33.10 Scrambling/Unscrambling Function 33.11 Automatic Wait States 33.11.1 Chip Select Wait States 33.11.2 Early Read Wait State 33.11.3 Reload User Configuration Wait State 33.11.3.1 User Procedure 33.11.3.2 Slow Clock Mode Transition 33.11.4 Read to Write Wait State 33.12 Data Float Wait States 33.12.1 READ_MODE 33.12.2 TDF Optimization Enabled (TDF_MODE = 1) 33.12.3 TDF Optimization Disabled (TDF_MODE = 0) 33.13 External Wait 33.13.1 Restriction 33.13.2 Frozen Mode 33.13.3 Ready Mode 33.13.4 NWAIT Latency and Read/Write Timings 33.14 Slow Clock Mode 33.14.1 Slow Clock Mode Waveforms 33.14.2 Switching from (to) Slow Clock Mode to (from) Normal Mode 33.15 Asynchronous Page Mode 33.15.1 Protocol and Timings in Page Mode 33.15.2 Page Mode Restriction 33.15.3 Sequential and Non-sequential Accesses 33.16 Static Memory Controller (SMC) User Interface 33.16.1 SMC Setup Register 33.16.2 SMC Pulse Register 33.16.3 SMC Cycle Register 33.16.4 SMC MODE Register 33.16.5 SMC OCMS Mode Register 33.16.6 SMC OCMS Key1 Register 33.16.7 SMC OCMS Key2 Register 33.16.8 SMC Write Protection Mode Register 33.16.9 SMC Write Protection Status Register 34. DMA Controller (XDMAC) 34.1 Description 34.2 Embedded Characteristics 34.3 DMA Controller Peripheral Connections 34.4 Block Diagram 34.5 Functional Description 34.5.1 Basic Definitions 34.5.2 Transfer Hierarchy Diagram 34.5.3 Peripheral Synchronized Transfer 34.5.3.1 Software Triggered Synchronized Transfer 34.5.4 XDMAC Transfer Software Operation 34.5.4.1 Single Block With Single Microblock Transfer 34.5.4.2 Single Block Transfer With Multiple Microblock 34.5.4.3 Master Transfer 34.5.4.4 Disabling A Channel Before Transfer Completion 34.6 Linked List Descriptor Operation 34.6.1 Linked List Descriptor View 34.6.1.1 Channel Next Descriptor View 0–3 Structures 34.6.2 Descriptor Structure Members Description 34.6.2.1 Descriptor Structure Microblock Control Member 34.7 XDMAC Maintenance Software Operations 34.7.1 Disabling a Channel 34.7.2 Suspending a Channel 34.7.3 Flushing a Channel 34.7.4 Maintenance Operation Priority 34.7.4.1 Disable Operation Priority 34.7.4.2 Flush Operation Priority 34.7.4.3 Suspend Operation Priority 34.8 XDMAC Software Requirements 34.9 Extensible DMA Controller (XDMAC) User Interface 34.9.1 XDMAC Global Type Register 34.9.2 XDMAC Global Configuration Register 34.9.3 XDMAC Global Weighted Arbiter Configuration Register 34.9.4 XDMAC Global Interrupt Enable Register 34.9.5 XDMAC Global Interrupt Disable Register 34.9.6 XDMAC Global Interrupt Mask Register 34.9.7 XDMAC Global Interrupt Status Register 34.9.8 XDMAC Global Channel Enable Register 34.9.9 XDMAC Global Channel Disable Register 34.9.10 XDMAC Global Channel Status Register 34.9.11 XDMAC Global Channel Read Suspend Register 34.9.12 XDMAC Global Channel Write Suspend Register 34.9.13 XDMAC Global Channel Read Write Suspend Register 34.9.14 XDMAC Global Channel Read Write Resume Register 34.9.15 XDMAC Global Channel Software Request Register 34.9.16 XDMAC Global Channel Software Request Status Register 34.9.17 XDMAC Global Channel Software Flush Request Register 34.9.18 XDMAC Channel x [x = 0..23] Interrupt Enable Register 34.9.19 XDMAC Channel x [x = 0..23] Interrupt Disable Register 34.9.20 XDMAC Channel x [x = 0..23] Interrupt Mask Register 34.9.21 XDMAC Channel x [x = 0..23] Interrupt Status Register 34.9.22 XDMAC Channel x [x = 0..23] Source Address Register 34.9.23 XDMAC Channel x [x = 0..23] Destination Address Register 34.9.24 XDMAC Channel x [x = 0..23] Next Descriptor Address Register 34.9.25 XDMAC Channel x [x = 0..23] Next Descriptor Control Register 34.9.26 XDMAC Channel x [x = 0..23] Microblock Control Register 34.9.27 XDMAC Channel x [x = 0..23] Block Control Register 34.9.28 XDMAC Channel x [x = 0..23] Configuration Register 34.9.29 XDMAC Channel x [x = 0..23] Data Stride Memory Set Pattern Register 34.9.30 XDMAC Channel x [x = 0..23] Source Microblock Stride Register 34.9.31 XDMAC Channel x [x = 0..23] Destination Microblock Stride Register 35. Image Sensor Interface (ISI) 35.1 Description 35.2 Embedded Characteristics 35.3 Block Diagram 35.4 Product Dependencies 35.4.1 I/O Lines 35.4.2 Power Management 35.4.3 Interrupt Sources 35.5 Functional Description 35.5.1 Data Timing 35.5.1.1 VSYNC/HSYNC Data Timing 35.5.1.2 SAV/EAV Data Timing 35.5.2 Data Ordering 35.5.3 Clocks 35.5.4 Preview Path 35.5.4.1 Scaling, Decimation (Subsampling) 35.5.4.2 Color Space Conversion 35.5.4.3 Memory Interface RGB Mode 12-bit Grayscale Mode 8-bit Grayscale Mode 35.5.4.4 FIFO and DMA Features 35.5.5 Codec Path 35.5.5.1 Color Space Conversion 35.5.5.2 Memory Interface 35.5.5.3 DMA Features 35.6 Image Sensor Interface (ISI) User Interface 35.6.1 ISI Configuration 1 Register 35.6.2 ISI Configuration 2 Register 35.6.3 ISI Preview Size Register 35.6.4 ISI Preview Decimation Factor Register 35.6.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register 35.6.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register 35.6.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register 35.6.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register 35.6.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register 35.6.10 ISI Control Register 35.6.11 ISI Status Register 35.6.12 ISI Interrupt Enable Register 35.6.13 ISI Interrupt Disable Register 35.6.14 ISI Interrupt Mask Register 35.6.15 DMA Channel Enable Register 35.6.16 DMA Channel Disable Register 35.6.17 DMA Channel Status Register 35.6.18 DMA Preview Base Address Register 35.6.19 DMA Preview Control Register 35.6.20 DMA Preview Descriptor Address Register 35.6.21 DMA Codec Base Address Register 35.6.22 DMA Codec Control Register 35.6.23 DMA Codec Descriptor Address Register 35.6.24 ISI Write Protection Mode Register 35.6.25 ISI Write Protection Status Register 36. USB High-Speed Interface (USBHS) 36.1 Description 36.2 Embedded Characteristics 36.3 Block Diagram 36.3.1 Signal Description 36.4 Product Dependencies 36.4.1 Clocks 36.4.2 Interrupt Sources 36.4.3 USB Pipe/Endpoint x FIFO Data Register (USBFIFOxDATA) 36.5 Functional Description 36.5.1 USB General Operation 36.5.1.1 Power-On and Reset 36.5.1.2 Interrupts 36.5.1.3 MCU Power Modes USB Suspend Mode Clock Frozen 36.5.1.4 Speed Control Device Mode Host Mode 36.5.1.5 DPRAM Management 36.5.1.6 Pad Suspend 36.5.2 USB Device Operation 36.5.2.1 Introduction 36.5.2.2 Power-On and Reset 36.5.2.3 USB Reset 36.5.2.4 Endpoint Reset 36.5.2.5 Endpoint Activation 36.5.2.6 Address Setup 36.5.2.7 Suspend and Wake-up 36.5.2.8 Detach 36.5.2.9 Remote Wake-up 36.5.2.10 STALL Request Special Considerations for Control Endpoints STALL Handshake and Retry Mechanism 36.5.2.11 Management of Control Endpoints Overview Control Write Control Read 36.5.2.12 Management of IN Endpoints Overview Detailed Description 36.5.2.13 Management of OUT Endpoints Overview Detailed Description 36.5.2.14 Underflow 36.5.2.15 Overflow 36.5.2.16 HB IsoIn Error 36.5.2.17 HB IsoFlush 36.5.2.18 CRC Error 36.5.2.19 Interrupts Global Interrupts Endpoint Interrupts DMA Interrupts 36.5.2.20 Test Modes 36.5.3 USB Host Operation 36.5.3.1 Description of Pipes 36.5.3.2 Power-On and Reset 36.5.3.3 Device Detection 36.5.3.4 USB Reset 36.5.3.5 Pipe Reset 36.5.3.6 Pipe Activation 36.5.3.7 Address Setup 36.5.3.8 Remote Wake-up 36.5.3.9 Management of Control Pipes 36.5.3.10 Management of IN Pipes 36.5.3.11 Management of OUT Pipes 36.5.3.12 CRC Error 36.5.3.13 Interrupts Global Interrupts Pipe Interrupts DMA Interrupts 36.5.4 USB DMA Operation 36.5.5 USB DMA Channel Transfer Descriptor 36.6 USB High-Speed (USBHS) User Interface 36.6.1 General Control Register 36.6.2 General Status Register 36.6.3 General Status Clear Register 36.6.4 General Status Set Register 36.6.5 Device General Control Register 36.6.6 Device Global Interrupt Status Register 36.6.7 Device Global Interrupt Clear Register 36.6.8 Device Global Interrupt Set Register 36.6.9 Device Global Interrupt Mask Register 36.6.10 Device Global Interrupt Disable Register 36.6.11 Device Global Interrupt Enable Register 36.6.12 Device Endpoint Register 36.6.13 Device Frame Number Register 36.6.14 Device Endpoint x Configuration Register 36.6.15 Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints) 36.6.16 Device Endpoint x Status Register (Isochronous Endpoints) 36.6.17 Device Endpoint x Clear Register (Control, Bulk, Interrupt Endpoints) 36.6.18 Device Endpoint x Clear Register (Isochronous Endpoints) 36.6.19 Device Endpoint x Set Register (Control, Bulk, Interrupt Endpoints) 36.6.20 Device Endpoint x Set Register (Isochronous Endpoints) 36.6.21 Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints) 36.6.22 Device Endpoint x Mask Register (Isochronous Endpoints) 36.6.23 Device Endpoint x Disable Register (Control, Bulk, Interrupt Endpoints) 36.6.24 Device Endpoint x Disable Register (Isochronous Endpoints) 36.6.25 Device Endpoint x Enable Register (Control, Bulk, Interrupt Endpoints) 36.6.26 Device Endpoint x Enable Register (Isochronous Endpoints) 36.6.27 Device DMA Channel x Next Descriptor Address Register 36.6.28 Device DMA Channel x Address Register 36.6.29 Device DMA Channel x Control Register 36.6.30 Device DMA Channel x Status Register 36.6.31 Host General Control Register 36.6.32 Host Global Interrupt Status Register 36.6.33 Host Global Interrupt Clear Register 36.6.34 Host Global Interrupt Set Register 36.6.35 Host Global Interrupt Mask Register 36.6.36 Host Global Interrupt Disable Register 36.6.37 Host Global Interrupt Enable Register 36.6.38 Host Frame Number Register 36.6.39 Host Address 1 Register 36.6.40 Host Address 2 Register 36.6.41 Host Address 3 Register 36.6.42 Host Pipe Register 36.6.43 Host Pipe x Configuration Register 36.6.44 Host Pipe x Configuration Register (High-speed Bulk-out or High-speed Control Pipe) 36.6.45 Host Pipe x Status Register (Control, Bulk Pipes) 36.6.46 Host Pipe x Status Register (Interrupt Pipes) 36.6.47 Host Pipe x Status Register (Isochronous Pipes) 36.6.48 Host Pipe x Clear Register (Control, Bulk Pipes) 36.6.49 Host Pipe x Clear Register (Interrupt Pipes) 36.6.50 Host Pipe x Clear Register (Isochronous Pipes) 36.6.51 Host Pipe x Set Register (Control, Bulk Pipes) 36.6.52 Host Pipe x Set Register (Interrupt Pipes) 36.6.53 Host Pipe x Set Register (Isochronous Pipes) 36.6.54 Host Pipe x Mask Register (Control, Bulk Pipes) 36.6.55 Host Pipe x Mask Register (Interrupt Pipes) 36.6.56 Host Pipe x Mask Register (Isochronous Pipes) 36.6.57 Host Pipe x Disable Register (Control, Bulk Pipes) 36.6.58 Host Pipe x Disable Register (Interrupt Pipes) 36.6.59 Host Pipe x Disable Register (Isochronous Pipes) 36.6.60 Host Pipe x Enable Register (Control, Bulk Pipes) 36.6.61 Host Pipe x Enable Register (Interrupt Pipes) 36.6.62 Host Pipe x Enable Register (Isochronous Pipes) 36.6.63 Host Pipe x IN Request Register 36.6.64 Host Pipe x Error Register 36.6.65 Host DMA Channel x Next Descriptor Address Register 36.6.66 Host DMA Channel x Address Register 36.6.67 Host DMA Channel x Control Register 36.6.68 Host DMA Channel x Status Register 37. Ethernet MAC (GMAC) 37.1 Description 37.2 Embedded Characteristics 37.3 Block Diagram 37.4 Signal Interfaces 37.5 Product Dependencies 37.5.1 I/O Lines 37.5.2 Power Management 37.5.3 Interrupt Sources 37.6 Functional Description 37.6.1 Media Access Controller 37.6.2 1588 Time Stamp Unit 37.6.3 AHB Direct Memory Access Interface 37.6.3.1 Packet Buffer DMA 37.6.3.2 Partial Store and Forward Using Packet Buffer DMA 37.6.3.3 Receive AHB Buffers 37.6.3.4 Transmit AHB Buffers 37.6.3.5 DMA Bursting on the AHB 37.6.3.6 DMA Packet Buffer 37.6.3.7 Transmit Packet Buffer 37.6.3.8 Receive Packet Buffer 37.6.3.9 Priority Queueing in the DMA 37.6.4 MAC Transmit Block 37.6.5 MAC Receive Block 37.6.6 Checksum Offload for IP, TCP and UDP 37.6.6.1 Receiver Checksum Offload 37.6.6.2 Transmitter Checksum Offload 37.6.7 MAC Filtering Block 37.6.8 Broadcast Address 37.6.9 Hash Addressing 37.6.10 Copy all Frames (Promiscuous Mode) 37.6.11 Disable Copy of Pause Frames 37.6.12 VLAN Support 37.6.13 Wake on LAN Support 37.6.14 IEEE 1588 Support 37.6.15 Time Stamp Unit 37.6.16 MAC 802.3 Pause Frame Support 37.6.16.1 802.3 Pause Frame Reception 37.6.16.2 802.3 Pause Frame Transmission 37.6.17 MAC PFC Priority-based Pause Frame Support 37.6.17.1 PFC Pause Frame Reception 37.6.17.2 PFC Pause Frame Transmission 37.6.18 802.1Qav Support - Credit-based Shaping 37.6.19 PHY Interface 37.6.20 10/100 Operation 37.6.21 Jumbo Frames 37.7 Programming Interface 37.7.1 Initialization 37.7.1.1 Configuration 37.7.1.2 Receive Buffer List 37.7.1.3 Transmit Buffer List 37.7.1.4 Address Matching 37.7.1.5 PHY Maintenance 37.7.1.6 Interrupts 37.7.1.7 Transmitting Frames 37.7.1.8 Receiving Frames 37.7.2 Statistics Registers 37.8 Ethernet MAC (GMAC) User Interface 37.8.1 GMAC Network Control Register 37.8.2 GMAC Network Configuration Register 37.8.3 GMAC Network Status Register 37.8.4 GMAC User Register 37.8.5 GMAC DMA Configuration Register 37.8.6 GMAC Transmit Status Register 37.8.7 GMAC Receive Buffer Queue Base Address Register 37.8.8 GMAC Transmit Buffer Queue Base Address Register 37.8.9 GMAC Receive Status Register 37.8.10 GMAC Interrupt Status Register 37.8.11 GMAC Interrupt Enable Register 37.8.12 GMAC Interrupt Disable Register 37.8.13 GMAC Interrupt Mask Register 37.8.14 GMAC PHY Maintenance Register 37.8.15 GMAC Receive Pause Quantum Register 37.8.16 GMAC Transmit Pause Quantum Register 37.8.17 GMAC TX Partial Store and Forward Register 37.8.18 GMAC RX Partial Store and Forward Register 37.8.19 GMAC RX Jumbo Frame Max Length Register 37.8.20 GMAC Hash Register Bottom 37.8.21 GMAC Hash Register Top 37.8.22 GMAC Specific Address 1 Bottom Register 37.8.23 GMAC Specific Address 1 Top Register 37.8.24 GMAC Specific Address 2 Bottom Register 37.8.25 GMAC Specific Address 2 Top Register 37.8.26 GMAC Specific Address 3 Bottom Register 37.8.27 GMAC Specific Address 3 Top Register 37.8.28 GMAC Specific Address 4 Bottom Register 37.8.29 GMAC Specific Address 4 Top Register 37.8.30 GMAC Type ID Match 1 Register 37.8.31 GMAC Type ID Match 2 Register 37.8.32 GMAC Type ID Match 3 Register 37.8.33 GMAC Type ID Match 4 Register 37.8.34 GMAC Wake on LAN Register 37.8.35 GMAC IPG Stretch Register 37.8.36 GMAC Stacked VLAN Register 37.8.37 GMAC Transmit PFC Pause Register 37.8.38 GMAC Specific Address 1 Mask Bottom Register 37.8.39 GMAC Specific Address Mask 1 Top Register 37.8.40 GMAC 1588 Timer Nanosecond Comparison Register 37.8.41 GMAC 1588 Timer Second Comparison Low Register 37.8.42 GMAC 1588 Timer Second Comparison High Register 37.8.43 GMAC PTP Event Frame Transmitted Seconds High Register 37.8.44 GMAC PTP Event Frame Received Seconds High Register 37.8.45 GMAC PTP Peer Event Frame Transmitted Seconds High Register 37.8.46 GMAC PTP Peer Event Frame Received Seconds High Register 37.8.47 GMAC Octets Transmitted Low Register 37.8.48 GMAC Octets Transmitted High Register 37.8.49 GMAC Frames Transmitted Register 37.8.50 GMAC Broadcast Frames Transmitted Register 37.8.51 GMAC Multicast Frames Transmitted Register 37.8.52 GMAC Pause Frames Transmitted Register 37.8.53 GMAC 64 Byte Frames Transmitted Register 37.8.54 GMAC 65 to 127 Byte Frames Transmitted Register 37.8.55 GMAC 128 to 255 Byte Frames Transmitted Register 37.8.56 GMAC 256 to 511 Byte Frames Transmitted Register 37.8.57 GMAC 512 to 1023 Byte Frames Transmitted Register 37.8.58 GMAC 1024 to 1518 Byte Frames Transmitted Register 37.8.59 GMAC Greater Than 1518 Byte Frames Transmitted Register 37.8.60 GMAC Transmit Underruns Register 37.8.61 GMAC Single Collision Frames Register 37.8.62 GMAC Multiple Collision Frames Register 37.8.63 GMAC Excessive Collisions Register 37.8.64 GMAC Late Collisions Register 37.8.65 GMAC Deferred Transmission Frames Register 37.8.66 GMAC Carrier Sense Errors Register 37.8.67 GMAC Octets Received Low Register 37.8.68 GMAC Octets Received High Register 37.8.69 GMAC Frames Received Register 37.8.70 GMAC Broadcast Frames Received Register 37.8.71 GMAC Multicast Frames Received Register 37.8.72 GMAC Pause Frames Received Register 37.8.73 GMAC 64 Byte Frames Received Register 37.8.74 GMAC 65 to 127 Byte Frames Received Register 37.8.75 GMAC 128 to 255 Byte Frames Received Register 37.8.76 GMAC 256 to 511 Byte Frames Received Register 37.8.77 GMAC 512 to 1023 Byte Frames Received Register 37.8.78 GMAC 1024 to 1518 Byte Frames Received Register 37.8.79 GMAC 1519 to Maximum Byte Frames Received Register 37.8.80 GMAC Undersized Frames Received Register 37.8.81 GMAC Oversized Frames Received Register 37.8.82 GMAC Jabbers Received Register 37.8.83 GMAC Frame Check Sequence Errors Register 37.8.84 GMAC Length Field Frame Errors Register 37.8.85 GMAC Receive Symbol Errors Register 37.8.86 GMAC Alignment Errors Register 37.8.87 GMAC Receive Resource Errors Register 37.8.88 GMAC Receive Overruns Register 37.8.89 GMAC IP Header Checksum Errors Register 37.8.90 GMAC TCP Checksum Errors Register 37.8.91 GMAC UDP Checksum Errors Register 37.8.92 GMAC 1588 Timer Increment Sub-nanoseconds Register 37.8.93 GMAC 1588 Timer Seconds High Register 37.8.94 GMAC 1588 Timer Seconds Low Register 37.8.95 GMAC 1588 Timer Nanoseconds Register 37.8.96 GMAC 1588 Timer Adjust Register 37.8.97 GMAC 1588 Timer Increment Register 37.8.98 GMAC PTP Event Frame Transmitted Seconds Low Register 37.8.99 GMAC PTP Event Frame Transmitted Nanoseconds Register 37.8.100 GMAC PTP Event Frame Received Seconds Low Register 37.8.101 GMAC PTP Event Frame Received Nanoseconds Register 37.8.102 GMAC PTP Peer Event Frame Transmitted Seconds Low Register 37.8.103 GMAC PTP Peer Event Frame Transmitted Nanoseconds Register 37.8.104 GMAC PTP Peer Event Frame Received Seconds Low Register 37.8.105 GMAC PTP Peer Event Frame Received Nanoseconds Register 37.8.106 GMAC Interrupt Status Register Priority Queue x 37.8.107 GMAC Transmit Buffer Queue Base Address Register Priority Queue x 37.8.108 GMAC Receive Buffer Queue Base Address Register Priority Queue x 37.8.109 GMAC Receive Buffer Size Register Priority Queue x 37.8.110 GMAC Credit-Based Shaping Control Register 37.8.111 GMAC Credit-Based Shaping IdleSlope Register for Queue A 37.8.112 GMAC Credit-Based Shaping IdleSlope Register for Queue B 37.8.113 GMAC Screening Type 1 Register x Priority Queue 37.8.114 GMAC Screening Type 2 Register x Priority Queue 37.8.115 GMAC Interrupt Enable Register Priority Queue x 37.8.116 GMAC Interrupt Disable Register Priority Queue x 37.8.117 GMAC Interrupt Mask Register Priority Queue x 37.8.118 GMAC Screening Type 2 EtherType Register x 37.8.119 GMAC Screening Type 2 Compare Word 0 Register x 37.8.120 GMAC Screening Type 2 Compare Word 1 Register x 38. High Speed Multimedia Card Interface (HSMCI) 38.1 Description 38.2 Embedded Characteristics 38.3 Block Diagram 38.4 Application Block Diagram 38.5 Pin Name List 38.6 Product Dependencies 38.6.1 I/O Lines 38.6.2 Power Management 38.6.3 Interrupt Sources 38.7 Bus Topology 38.8 High Speed MultiMedia Card Operations 38.8.1 Command - Response Operation 38.8.2 Data Transfer Operation 38.8.3 Read Operation 38.8.4 Write Operation 38.8.5 WRITE_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK Operation using DMA Controller 38.8.6 READ_SINGLE_BLOCK/READ_MULTIPLE_BLOCK Operation using DMA Controller 38.9 SD/SDIO Card Operation 38.9.1 SDIO Data Transfer Type 38.9.2 SDIO Interrupts 38.10 CE-ATA Operation 38.10.1 Executing an ATA Polling Command 38.10.2 Executing an ATA Interrupt Command 38.10.3 Aborting an ATA Command 38.10.4 CE-ATA Error Recovery 38.11 HSMCI Boot Operation Mode 38.11.1 Boot Procedure, Processor Mode 38.11.2 Boot Procedure DMA Mode 38.12 HSMCI Transfer Done Timings 38.12.1 Definition 38.12.2 Read Access 38.12.3 Write Access 38.13 Register Write Protection 38.14 High Speed MultiMedia Card Interface (HSMCI) User Interface 38.14.1 HSMCI Control Register 38.14.2 HSMCI Mode Register 38.14.3 HSMCI Data Timeout Register 38.14.4 HSMCI SDCard/SDIO Register 38.14.5 HSMCI Argument Register 38.14.6 HSMCI Command Register 38.14.7 HSMCI Block Register 38.14.8 HSMCI Completion Signal Timeout Register 38.14.9 HSMCI Response Register 38.14.10 HSMCI Receive Data Register 38.14.11 HSMCI Transmit Data Register 38.14.12 HSMCI Status Register 38.14.13 HSMCI Interrupt Enable Register 38.14.14 HSMCI Interrupt Disable Register 38.14.15 HSMCI Interrupt Mask Register 38.14.16 HSMCI DMA Configuration Register 38.14.17 HSMCI Configuration Register 38.14.18 HSMCI Write Protection Mode Register 38.14.19 HSMCI Write Protection Status Register 38.14.20 HSMCI FIFOx Memory Aperture 39. Quad SPI Interface (QSPI) 39.1 Description 39.2 Embedded Characteristics 39.3 Block Diagram 39.4 Signal Description 39.5 Product Dependencies 39.5.1 I/O Lines 39.5.2 Power Management 39.5.3 Interrupt Sources 39.5.4 Direct Memory Access Controller (DMA) 39.6 Functional Description 39.6.1 Serial Clock Baudrate 39.6.2 Serial Clock Phase and Polarity 39.6.3 Transfer Delays 39.6.4 QSPI SPI Mode 39.6.4.1 SPI Mode Operations 39.6.4.2 SPI Mode Block Diagram 39.6.4.3 SPI Mode Flow Diagram 39.6.4.4 Peripheral Deselection without DMA 39.6.4.5 Peripheral Deselection with DMA 39.6.5 QSPI Serial Memory Mode 39.6.5.1 Instruction Frame 39.6.5.2 Instruction Frame Transmission 39.6.5.3 Read Memory Transfer 39.6.5.4 Continuous Read Mode 39.6.5.5 Instruction Frame Transmission Examples 39.6.6 Scrambling/Unscrambling Function 39.6.7 Register Write Protection 39.7 Quad SPI Interface (QSPI) User Interface 39.7.1 QSPI Control Register 39.7.2 QSPI Mode Register 39.7.3 QSPI Receive Data Register 39.7.4 QSPI Transmit Data Register 39.7.5 QSPI Status Register 39.7.6 QSPI Interrupt Enable Register 39.7.7 QSPI Interrupt Disable Register 39.7.8 QSPI Interrupt Mask Register 39.7.9 QSPI Serial Clock Register 39.7.10 QSPI Instruction Address Register 39.7.11 QSPI Instruction Code Register 39.7.12 QSPI Instruction Frame Register 39.7.13 QSPI Scrambling Mode Register 39.7.14 QSPI Scrambling Key Register 39.7.15 QSPI Write Protection Mode Register 39.7.16 QSPI Write Protection Status Register 40. Serial Peripheral Interface (SPI) 40.1 Description 40.2 Embedded Characteristics 40.3 Block Diagram 40.4 Application Block Diagram 40.5 Signal Description 40.6 Product Dependencies 40.6.1 I/O Lines 40.6.2 Power Management 40.6.3 Interrupt 40.6.4 Direct Memory Access Controller (DMAC) 40.7 Functional Description 40.7.1 Modes of Operation 40.7.2 Data Transfer 40.7.3 Master Mode Operations 40.7.3.1 Master Mode Block Diagram 40.7.3.2 Master Mode Flow Diagram 40.7.3.3 Clock Generation 40.7.3.4 Transfer Delays 40.7.3.5 Peripheral Selection 40.7.3.6 SPI Direct Access Memory Controller (DMAC) 40.7.3.7 Peripheral Chip Select Decoding 40.7.3.8 Peripheral Deselection without DMA 40.7.3.9 Peripheral Deselection with DMA 40.7.3.10 Mode Fault Detection 40.7.4 SPI Slave Mode 40.7.5 Register Write Protection 40.8 Serial Peripheral Interface (SPI) User Interface 40.8.1 SPI Control Register 40.8.2 SPI Mode Register 40.8.3 SPI Receive Data Register 40.8.4 SPI Transmit Data Register 40.8.5 SPI Status Register 40.8.6 SPI Interrupt Enable Register 40.8.7 SPI Interrupt Disable Register 40.8.8 SPI Interrupt Mask Register 40.8.9 SPI Chip Select Register 40.8.10 SPI Write Protection Mode Register 40.8.11 SPI Write Protection Status Register 41. Two-wire Interface (TWIHS) 41.1 Description 41.2 Embedded Characteristics 41.3 List of Abbreviations 41.4 Block Diagram 41.4.1 I/O Lines Description 41.5 Product Dependencies 41.5.1 I/O Lines 41.5.2 Power Management 41.5.3 Interrupt Sources 41.6 Functional Description 41.6.1 Transfer Format 41.6.2 Modes of Operation 41.6.3 Master Mode 41.6.3.1 Definition 41.6.3.2 Programming Master Mode 41.6.3.3 Master Transmitter Mode 41.6.3.4 Master Receiver Mode 41.6.3.5 Internal Address 7-bit Slave Addressing 10-bit Slave Addressing 41.6.3.6 Repeated Start 41.6.3.7 Bus Clear Command 41.6.3.8 Using the DMA Controller (DMAC) in Master Mode Data Transmit with the DMA in Master Mode Data Receive with the DMA in Master Mode 41.6.3.9 SMBus Mode Packet Error Checking Timeouts 41.6.3.10 SMBus Quick Command (Master Mode Only) 41.6.3.11 Read/Write Flowcharts 41.6.4 Multi-master Mode 41.6.4.1 Definition 41.6.4.2 Different Multi-master Modes TWIHS as Master Only TWIHS as Master or Slave 41.6.5 Slave Mode 41.6.5.1 Definition 41.6.5.2 Programming Slave Mode 41.6.5.3 Receiving Data Read Sequence Write Sequence Clock Stretching Sequence General Call 41.6.5.4 Data Transfer Read Operation Write Operation General Call Clock Stretching Clock Stretching in Read Mode Clock Stretching in Write Mode Reversal after a Repeated Start Reversal of Read to Write Reversal of Write to Read 41.6.5.5 Using the DMA Controller (DMAC) in Slave Mode Data Transmit with the DMA in Slave Mode Data Receive with the DMA in Slave Mode 41.6.5.6 SMBus Mode Packet Error Checking Timeouts 41.6.5.7 High-Speed Slave Mode Read/Write Operation Usage 41.6.5.8 Asynchronous Partial Wake-up (SleepWalking) 41.6.5.9 Slave Read Write Flowcharts 41.6.6 TWIHS Comparison Function on Received Character 41.6.7 Register Write Protection 41.7 Two-wire Interface High Speed (TWIHS) User Interface 41.7.1 TWIHS Control Register 41.7.2 TWIHS Master Mode Register 41.7.3 TWIHS Slave Mode Register 41.7.4 TWIHS Internal Address Register 41.7.5 TWIHS Clock Waveform Generator Register 41.7.6 TWIHS Status Register 41.7.7 TWIHS SMBus Timing Register 41.7.8 TWIHS Filter Register 41.7.9 TWIHS Interrupt Enable Register 41.7.10 TWIHS Interrupt Disable Register 41.7.11 TWIHS Interrupt Mask Register 41.7.12 TWIHS Receive Holding Register 41.7.13 TWIHS SleepWalking Matching Register 41.7.14 TWIHS Transmit Holding Register 41.7.15 TWIHS Write Protection Mode Register 41.7.16 TWIHS Write Protection Status Register 42. Synchronous Serial Controller (SSC) 42.1 Description 42.2 Embedded Characteristics 42.3 Block Diagram 42.4 Application Block Diagram 42.5 SSC Application Examples 42.6 Pin Name List 42.7 Product Dependencies 42.7.1 I/O Lines 42.7.2 Power Management 42.7.3 Interrupt 42.8 Functional Description 42.8.1 Clock Management 42.8.1.1 Clock Divider 42.8.1.2 Transmitter Clock Management 42.8.1.3 Receiver Clock Management 42.8.1.4 Serial Clock Ratio Considerations 42.8.2 Transmitter Operations 42.8.3 Receiver Operations 42.8.4 Start 42.8.5 Frame Sync 42.8.5.1 Frame Sync Data 42.8.5.2 Frame Sync Edge Detection 42.8.6 Receive Compare Modes 42.8.6.1 Compare Functions 42.8.7 Data Format 42.8.8 Loop Mode 42.8.9 Interrupt 42.8.10 Register Write Protection 42.9 Synchronous Serial Controller (SSC) User Interface 42.9.1 SSC Control Register 42.9.2 SSC Clock Mode Register 42.9.3 SSC Receive Clock Mode Register 42.9.4 SSC Receive Frame Mode Register 42.9.5 SSC Transmit Clock Mode Register 42.9.6 SSC Transmit Frame Mode Register 42.9.7 SSC Receive Holding Register 42.9.8 SSC Transmit Holding Register 42.9.9 SSC Receive Synchronization Holding Register 42.9.10 SSC Transmit Synchronization Holding Register 42.9.11 SSC Receive Compare 0 Register 42.9.12 SSC Receive Compare 1 Register 42.9.13 SSC Status Register 42.9.14 SSC Interrupt Enable Register 42.9.15 SSC Interrupt Disable Register 42.9.16 SSC Interrupt Mask Register 42.9.17 SSC Write Protection Mode Register 42.9.18 SSC Write Protection Status Register 43. Universal Synchronous Asynchronous Receiver Transceiver (USART) 43.1 Description 43.2 Embedded Characteristics 43.3 Block Diagram 43.4 I/O Lines Description 43.5 Product Dependencies 43.5.1 I/O Lines 43.5.2 Power Management 43.5.3 Interrupt Sources 43.6 Functional Description 43.6.1 Baud Rate Generator 43.6.1.1 Baud Rate in Asynchronous Mode 43.6.1.2 Fractional Baud Rate in Asynchronous Mode 43.6.1.3 Baud Rate in Synchronous Mode or SPI Mode 43.6.2 Receiver and Transmitter Control 43.6.3 Synchronous and Asynchronous Modes 43.6.3.1 Transmitter Operations 43.6.3.2 Manchester Encoder 43.6.3.3 Asynchronous Receiver 43.6.3.4 Manchester Decoder 43.6.3.5 Radio Interface: Manchester Encoded USART Application 43.6.3.6 Synchronous Receiver 43.6.3.7 Receiver Operations 43.6.3.8 Parity 43.6.3.9 Multidrop Mode 43.6.3.10 Transmitter Timeguard 43.6.3.11 Receiver Time-out 43.6.3.12 Framing Error 43.6.3.13 Transmit Break 43.6.3.14 Receive Break 43.6.3.15 Hardware Handshaking 43.6.4 ISO7816 Mode 43.6.4.1 ISO7816 Mode Overview 43.6.4.2 Protocol T = 0 43.6.4.3 Protocol T = 1 43.6.5 RS485 Mode 43.6.6 SPI Mode 43.6.6.1 Modes of Operation 43.6.6.2 Baud Rate 43.6.6.3 Data Transfer 43.6.6.4 Receiver and Transmitter Control 43.6.6.5 Character Transmission 43.6.6.6 Character Reception 43.6.6.7 Receiver Timeout 43.6.7 LIN Mode 43.6.7.1 Modes of Operation 43.6.7.2 Baud Rate Configuration 43.6.7.3 Receiver and Transmitter Control 43.6.7.4 Character Transmission 43.6.7.5 Character Reception 43.6.7.6 Header Transmission (Master Node Configuration) 43.6.7.7 Header Reception (Slave Node Configuration) 43.6.7.8 Slave Node Synchronization 43.6.7.9 Identifier Parity 43.6.7.10 Node Action 43.6.7.11 Response Data Length 43.6.7.12 Checksum 43.6.7.13 Frame Slot Mode 43.6.7.14 LIN Errors 43.6.7.15 LIN Frame Handling 43.6.7.16 LIN Frame Handling with the DMAC 43.6.7.17 Wake-up Request 43.6.7.18 Bus Idle Time-out 43.6.8 LON Mode 43.6.8.1 Mode of Operation 43.6.8.2 Receiver and Transmitter Control 43.6.8.3 Character Transmission 43.6.8.4 Character Reception 43.6.8.5 LON Frame 43.6.8.6 LON Operating Modes 43.6.8.7 LON Node Backlog Estimation 43.6.8.8 LON Timings 43.6.8.9 LON Errors 43.6.8.10 Drift Compensation 43.6.8.11 LON Frame Handling 43.6.8.12 LON Frame Handling with the Peripheral DMA Controller 43.6.9 Test Modes 43.6.9.1 Normal Mode 43.6.9.2 Automatic Echo Mode 43.6.9.3 Local Loopback Mode 43.6.9.4 Remote Loopback Mode 43.6.10 Register Write Protection 43.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface 43.7.1 USART Control Register 43.7.2 USART Control Register (SPI_MODE) 43.7.3 USART Mode Register 43.7.4 USART Mode Register (SPI_MODE) 43.7.5 USART Interrupt Enable Register 43.7.6 USART Interrupt Enable Register (SPI_MODE) 43.7.7 USART Interrupt Enable Register (LIN_MODE) 43.7.8 USART Interrupt Enable Register (LON_MODE) 43.7.9 USART Interrupt Disable Register 43.7.10 USART Interrupt Disable Register (SPI_MODE) 43.7.11 USART Interrupt Disable Register (LIN_MODE) 43.7.12 USART Interrupt Disable Register (LON_MODE) 43.7.13 USART Interrupt Mask Register 43.7.14 USART Interrupt Mask Register (SPI_MODE) 43.7.15 USART Interrupt Mask Register (LIN_MODE) 43.7.16 USART Interrupt Mask Register (LON_MODE) 43.7.17 USART Channel Status Register 43.7.18 USART Channel Status Register (SPI_MODE) 43.7.19 USART Channel Status Register (LIN_MODE) 43.7.20 USART Channel Status Register (LON_MODE) 43.7.21 USART Receive Holding Register 43.7.22 USART Transmit Holding Register 43.7.23 USART Baud Rate Generator Register 43.7.24 USART Receiver Time-out Register 43.7.25 USART Transmitter Timeguard Register 43.7.26 USART Transmitter Timeguard Register (LON_MODE) 43.7.27 USART FI DI RATIO Register (LON_MODE) 43.7.28 USART Manchester Configuration Register 43.7.29 USART LIN Mode Register 43.7.30 USART LIN Identifier Register 43.7.31 USART LIN Baud Rate Register 43.7.32 USART LON Mode Register 43.7.33 USART LON Preamble Register 43.7.34 USART LON Data Length Register 43.7.35 USART LON L2HDR Register 43.7.36 USART LON Backlog Register 43.7.37 USART LON Beta1 Tx Register 43.7.38 USART LON Beta1 Rx Register 43.7.39 USART LON Priority Register 43.7.40 USART LON IDT Tx Register 43.7.41 USART LON IDT Rx Register 43.7.42 USART IC DIFF Register 43.7.43 USART Write Protection Mode Register 43.7.44 USART Write Protection Status Register 44. Universal Asynchronous Receiver Transmitter (UART) 44.1 Description 44.2 Embedded Characteristics 44.3 Block Diagram 44.4 Product Dependencies 44.4.1 I/O Lines 44.4.2 Power Management 44.4.3 Interrupt Sources 44.5 Functional Description 44.5.1 Baud Rate Generator 44.5.2 Receiver 44.5.2.1 Receiver Reset, Enable and Disable 44.5.2.2 Start Detection and Data Sampling 44.5.2.3 Receiver Ready 44.5.2.4 Receiver Overrun 44.5.2.5 Parity Error 44.5.2.6 Receiver Framing Error 44.5.2.7 Receiver Digital Filter 44.5.3 Transmitter 44.5.3.1 Transmitter Reset, Enable and Disable 44.5.3.2 Transmit Format 44.5.3.3 Transmitter Control 44.5.4 DMA Support 44.5.5 Comparison Function on Received Character 44.5.6 Asynchronous and Partial Wake-up (SleepWalking) 44.5.7 Register Write Protection 44.5.8 Test Modes 44.6 Universal Asynchronous Receiver Transmitter (UART) User Interface 44.6.1 UART Control Register 44.6.2 UART Mode Register 44.6.3 UART Interrupt Enable Register 44.6.4 UART Interrupt Disable Register 44.6.5 UART Interrupt Mask Register 44.6.6 UART Status Register 44.6.7 UART Receiver Holding Register 44.6.8 UART Transmit Holding Register 44.6.9 UART Baud Rate Generator Register 44.6.10 UART Comparison Register 44.6.11 UART Write Protection Mode Register 45. Controller Area Network (MCAN) 45.1 Description 45.2 Embedded Characteristics 45.3 Block Diagram 45.4 Product Dependencies 45.4.1 I/O Lines 45.4.2 Power Management 45.4.3 Interrupt Sources 45.4.4 Address Configuration 45.5 Functional Description 45.5.1 Operating Modes 45.5.1.1 Software Initialization 45.5.1.2 Normal Operation 45.5.1.3 CAN FD Operation 45.5.1.4 Transceiver Delay Compensation Description Configuration and Status 45.5.1.5 Restricted Operation Mode 45.5.1.6 Bus Monitoring Mode 45.5.1.7 Disabled Automatic Retransmission Frame Transmission in DAR Mode 45.5.1.8 Power Down (Sleep Mode) 45.5.1.9 Test Modes External Loop Back Mode Internal Loop Back Mode 45.5.2 Timestamp Generation 45.5.3 Timeout Counter 45.5.4 Rx Handling 45.5.4.1 Acceptance Filtering Range Filter Filter for Specific IDs Classic Bit Mask Filter Standard Message ID Filtering Extended Message ID Filtering 45.5.4.2 Rx FIFOs Rx FIFO Blocking Mode Rx FIFO Overwrite Mode 45.5.4.3 Dedicated Rx Buffers Rx Buffer Handling 45.5.4.4 Debug on CAN Support Filtering for Debug Messages Debug Message Handling 45.5.5 Tx Handling 45.5.5.1 Transmit Pause 45.5.5.2 Dedicated Tx Buffers 45.5.5.3 Tx FIFO 45.5.5.4 Tx Queue 45.5.5.5 Mixed Dedicated Tx Buffers / Tx FIFO 45.5.5.6 Mixed Dedicated Tx Buffers / Tx Queue 45.5.5.7 Transmit Cancellation 45.5.5.8 Tx Event Handling 45.5.6 FIFO Acknowledge Handling 45.5.7 Message RAM 45.5.7.1 Message RAM Configuration 45.5.7.2 Rx Buffer and FIFO Element 45.5.7.3 Tx Buffer Element 45.5.7.4 Tx Event FIFO Element 45.5.7.5 Standard Message ID Filter Element 45.5.7.6 Extended Message ID Filter Element 45.5.8 Hardware Reset Description 45.6 Controller Area Network (MCAN) User Interface 45.6.1 MCAN Customer Register 45.6.2 MCAN Fast Bit Timing and Prescaler Register 45.6.3 MCAN Test Register 45.6.4 MCAN RAM Watchdog Register 45.6.5 MCAN CC Control Register 45.6.6 MCAN Bit Timing and Prescaler Register 45.6.7 MCAN Timestamp Counter Configuration Register 45.6.8 MCAN Timestamp Counter Value Register 45.6.9 MCAN Timeout Counter Configuration Register 45.6.10 MCAN Timeout Counter Value Register 45.6.11 MCAN Error Counter Register 45.6.12 MCAN Protocol Status Register 45.6.13 MCAN Interrupt Register 45.6.14 MCAN Interrupt Enable Register 45.6.15 MCAN Interrupt Line Select Register 45.6.16 MCAN Interrupt Line Enable 45.6.17 MCAN Global Filter Configuration 45.6.18 MCAN Standard ID Filter Configuration 45.6.19 MCAN Extended ID Filter Configuration 45.6.20 MCAN Extended ID AND Mask 45.6.21 MCAN High Priority Message Status 45.6.22 MCAN New Data 1 45.6.23 MCAN New Data 2 45.6.24 MCAN Receive FIFO 0 Configuration 45.6.25 MCAN Receive FIFO 0 Status 45.6.26 MCAN Receive FIFO 0 Acknowledge 45.6.27 MCAN Receive Buffer Configuration 45.6.28 MCAN Receive FIFO 1 Configuration 45.6.29 MCAN Receive FIFO 1 Status 45.6.30 MCAN Receive FIFO 1 Acknowledge 45.6.31 MCAN Receive Buffer / FIFO Element Size Configuration 45.6.32 MCAN Tx Buffer Configuration 45.6.33 MCAN Tx FIFO/Queue Status 45.6.34 MCAN Tx Buffer Element Size Configuration 45.6.35 MCAN Transmit Buffer Request Pending 45.6.36 MCAN Transmit Buffer Add Request 45.6.37 MCAN Transmit Buffer Cancellation Request 45.6.38 MCAN Transmit Buffer Transmission Occurred 45.6.39 MCAN Transmit Buffer Cancellation Finished 45.6.40 MCAN Transmit Buffer Transmission Interrupt Enable 45.6.41 MCAN Transmit Buffer Cancellation Finished Interrupt Enable 45.6.42 MCAN Transmit Event FIFO Configuration 45.6.43 MCAN Tx Event FIFO Status 45.6.44 MCAN Tx Event FIFO Acknowledge 46. Timer Counter (TC) 46.1 Description 46.2 Embedded Characteristics 46.3 Block Diagram 46.4 Pin Name List 46.5 Product Dependencies 46.5.1 I/O Lines 46.5.2 Power Management 46.5.3 Interrupt Sources 46.5.4 Synchronization Inputs from PWM 46.5.5 Fault Output 46.6 Functional Description 46.6.1 Overview 46.6.2 16-bit Counter 46.6.3 Clock Selection 46.6.4 Clock Control 46.6.5 Operating Modes 46.6.6 Trigger 46.6.7 Capture Mode 46.6.8 Capture Registers A and B 46.6.9 Transfer with DMAC 46.6.10 Trigger Conditions 46.6.11 Waveform Mode 46.6.12 Waveform Selection 46.6.12.1 WAVSEL = 00 46.6.12.2 WAVSEL = 10 46.6.12.3 WAVSEL = 01 46.6.12.4 WAVSEL = 11 46.6.13 External Event/Trigger Conditions 46.6.14 Synchronization with PWM 46.6.15 Output Controller 46.6.16 Quadrature Decoder 46.6.16.1 Description 46.6.16.2 Input Pre-processing 46.6.16.3 Direction Status and Change Detection 46.6.16.4 Position and Rotation Measurement 46.6.16.5 Speed Measurement 46.6.17 2-bit Gray Up/Down Counter for Stepper Motor 46.6.18 Fault Mode 46.6.19 Register Write Protection 46.7 Timer Counter (TC) User Interface 46.7.1 TC Channel Control Register 46.7.2 TC Channel Mode Register: Capture Mode 46.7.3 TC Channel Mode Register: Waveform Mode 46.7.4 TC Stepper Motor Mode Register 46.7.5 TC Register AB 46.7.6 TC Counter Value Register 46.7.7 TC Register A 46.7.8 TC Register B 46.7.9 TC Register C 46.7.10 TC Status Register 46.7.11 TC Interrupt Enable Register 46.7.12 TC Interrupt Disable Register 46.7.13 TC Interrupt Mask Register 46.7.14 TC Extended Mode Register 46.7.15 TC Block Control Register 46.7.16 TC Block Mode Register 46.7.17 TC QDEC Interrupt Enable Register 46.7.18 TC QDEC Interrupt Disable Register 46.7.19 TC QDEC Interrupt Mask Register 46.7.20 TC QDEC Interrupt Status Register 46.7.21 TC Fault Mode Register 46.7.22 TC Write Protection Mode Register 47. Pulse Width Modulation Controller (PWM) 47.1 Description 47.2 Embedded Characteristics 47.3 Block Diagram 47.4 I/O Lines Description 47.5 Product Dependencies 47.5.1 I/O Lines 47.5.2 Power Management 47.5.3 Interrupt Sources 47.5.4 Fault Inputs 47.6 Functional Description 47.6.1 PWM Clock Generator 47.6.2 PWM Channel 47.6.2.1 Channel Block Diagram 47.6.2.2 Comparator 47.6.2.3 Trigger Selection for Timer Counter Delay Measurement Cumulated ON Time Measurement 47.6.2.4 2-bit Gray Up/Down Counter for Stepper Motor 47.6.2.5 Dead-Time Generator PWM Push-Pull Mode 47.6.2.6 Output Override 47.6.2.7 Fault Protection Recoverable Fault 47.6.2.8 Spread Spectrum Counter 47.6.2.9 Synchronous Channels Method 1: Manual write of duty-cycle values and manual trigger of the update Method 2: Manual write of duty-cycle values and automatic trigger of the update Method 3: Automatic write of duty-cycle values and automatic trigger of the update 47.6.2.10 Update Time for Double-Buffering Registers 47.6.3 PWM Comparison Units 47.6.4 PWM Event Lines 47.6.5 PWM External Trigger Mode 47.6.5.1 External PWM Reset Mode Application Example 47.6.5.2 External PWM Start Mode Application Example 47.6.5.3 Cycle-By-Cycle Duty Mode Description Application Example 47.6.5.4 Leading-Edge Blanking (LEB) 47.6.6 PWM Controller Operations 47.6.6.1 Initialization 47.6.6.2 Source Clock Selection Criteria 47.6.6.3 Changing the Duty-Cycle, the Period and the Dead-Times 47.6.6.4 Changing the Update Period of Synchronous Channels 47.6.6.5 Changing the Comparison Value and the Comparison Configuration 47.6.6.6 Interrupts 47.6.7 Register Write Protection 47.7 Pulse Width Modulation Controller (PWM) User Interface 47.7.1 PWM Clock Register 47.7.2 PWM Enable Register 47.7.3 PWM Disable Register 47.7.4 PWM Status Register 47.7.5 PWM Interrupt Enable Register 1 47.7.6 PWM Interrupt Disable Register 1 47.7.7 PWM Interrupt Mask Register 1 47.7.8 PWM Interrupt Status Register 1 47.7.9 PWM Sync Channels Mode Register 47.7.10 PWM DMA Register 47.7.11 PWM Sync Channels Update Control Register 47.7.12 PWM Sync Channels Update Period Register 47.7.13 PWM Sync Channels Update Period Update Register 47.7.14 PWM Interrupt Enable Register 2 47.7.15 PWM Interrupt Disable Register 2 47.7.16 PWM Interrupt Mask Register 2 47.7.17 PWM Interrupt Status Register 2 47.7.18 PWM Output Override Value Register 47.7.19 PWM Output Selection Register 47.7.20 PWM Output Selection Set Register 47.7.21 PWM Output Selection Clear Register 47.7.22 PWM Output Selection Set Update Register 47.7.23 PWM Output Selection Clear Update Register 47.7.24 PWM Fault Mode Register 47.7.25 PWM Fault Status Register 47.7.26 PWM Fault Clear Register 47.7.27 PWM Fault Protection Value Register 1 47.7.28 PWM Fault Protection Enable Register 47.7.29 PWM Event Line x Register 47.7.30 PWM Spread Spectrum Register 47.7.31 PWM Spread Spectrum Update Register 47.7.32 PWM Stepper Motor Mode Register 47.7.33 PWM Fault Protection Value Register 2 47.7.34 PWM Write Protection Control Register 47.7.35 PWM Write Protection Status Register 47.7.36 PWM Comparison x Value Register 47.7.37 PWM Comparison x Value Update Register 47.7.38 PWM Comparison x Mode Register 47.7.39 PWM Comparison x Mode Update Register 47.7.40 PWM Channel Mode Register 47.7.41 PWM Channel Duty Cycle Register 47.7.42 PWM Channel Duty Cycle Update Register 47.7.43 PWM Channel Period Register 47.7.44 PWM Channel Period Update Register 47.7.45 PWM Channel Counter Register 47.7.46 PWM Channel Dead Time Register 47.7.47 PWM Channel Dead Time Update Register 47.7.48 PWM Channel Mode Update Register 47.7.49 PWM External Trigger Register 47.7.50 PWM Leading-Edge Blanking Register 48. Analog Front-End Controller (AFEC) 48.1 Description 48.2 Embedded Characteristics 48.3 Block Diagram 48.4 Signal Description 48.5 Product Dependencies 48.5.1 I/O Lines 48.5.2 Power Management 48.5.3 Interrupt Sources 48.5.4 Temperature Sensor 48.5.5 Timer Triggers 48.5.6 PWM Event Line 48.5.7 Fault Output 48.5.8 Conversion Performances 48.6 Functional Description 48.6.1 Analog Front-End Conversion 48.6.2 Conversion Reference 48.6.3 Conversion Resolution 48.6.4 Conversion Results 48.6.5 Conversion Results Format 48.6.6 Conversion Triggers 48.6.7 Sleep Mode and Conversion Sequencer 48.6.8 Comparison Window 48.6.9 Differential Inputs 48.6.10 Sample-and-Hold Modes 48.6.11 Input Gain and Offset 48.6.12 AFE Timings 48.6.13 Temperature Sensor 48.6.14 Enhanced Resolution Mode and Digital Averaging Function 48.6.15 Automatic Error Correction 48.6.16 Buffer Structure 48.6.17 Fault Output 48.6.18 Register Write Protection 48.7 Analog Front-End Controller (AFEC) User Interface 48.7.1 AFEC Control Register 48.7.2 AFEC Mode Register 48.7.3 AFEC Extended Mode Register 48.7.4 AFEC Channel Sequence 1 Register 48.7.5 AFEC Channel Sequence 2 Register 48.7.6 AFEC Channel Enable Register 48.7.7 AFEC Channel Disable Register 48.7.8 AFEC Channel Status Register 48.7.9 AFEC Last Converted Data Register 48.7.10 AFEC Interrupt Enable Register 48.7.11 AFEC Interrupt Disable Register 48.7.12 AFEC Interrupt Mask Register 48.7.13 AFEC Interrupt Status Register 48.7.14 AFEC Overrun Status Register 48.7.15 AFEC Compare Window Register 48.7.16 AFEC Channel Gain Register 48.7.17 AFEC Channel Differential Register 48.7.18 AFEC Channel Selection Register 48.7.19 AFEC Channel Data Register 48.7.20 AFEC Channel Offset Compensation Register 48.7.21 AFEC Temperature Sensor Mode Register 48.7.22 AFEC Temperature Compare Window Register 48.7.23 AFEC Analog Control Register 48.7.24 AFEC Sample & Hold Mode Register 48.7.25 AFEC Correction Select Register 48.7.26 AFEC Correction Values Register 48.7.27 AFEC Channel Error Correction Register 48.7.28 AFEC Write Protection Mode Register 48.7.29 AFEC Write Protection Status Register 49. Digital-to-Analog Converter (DACC) 49.1 Description 49.2 Embedded Characteristics 49.3 Block Diagram 49.4 Signal Description 49.5 Product Dependencies 49.5.1 I/O Lines 49.5.2 Power Management 49.5.3 Interrupt Sources 49.5.4 Conversion Performances 49.6 Functional Description 49.6.1 Digital-to-Analog Conversion 49.6.2 Conversion Results 49.6.3 Analog Output Mode Selection 49.6.4 Conversion Modes 49.6.4.1 Free-Running Mode 49.6.4.2 Max Speed Mode 49.6.4.3 External Trigger Mode 49.6.4.4 Interpolation Mode 49.6.5 Conversion FIFO 49.6.6 DACC Timings 49.6.7 Register Write Protection 49.7 Digital-to-Analog Converter (DACC) User Interface 49.7.1 DACC Control Register 49.7.2 DACC Mode Register 49.7.3 DACC Trigger Register 49.7.4 DACC Channel Enable Register 49.7.5 DACC Channel Disable Register 49.7.6 DACC Channel Status Register 49.7.7 DACC Conversion Data Register 49.7.8 DACC Interrupt Enable Register 49.7.9 DACC Interrupt Disable Register 49.7.10 DACC Interrupt Mask Register 49.7.11 DACC Interrupt Status Register 49.7.12 DACC Analog Current Register 49.7.13 DACC Write Protection Mode Register 49.7.14 DACC Write Protection Status Register 50. Analog Comparator Controller (ACC) 50.1 Description 50.2 Embedded Characteristics 50.3 Block Diagram 50.4 Signal Description 50.5 Product Dependencies 50.5.1 I/O Lines 50.5.2 Power Management 50.5.3 Interrupt Sources 50.5.4 Fault Output 50.6 Functional Description 50.6.1 Description 50.6.2 Analog Settings 50.6.3 Output Masking Period 50.6.4 Fault Mode 50.6.5 Register Write Protection 50.7 Analog Comparator Controller (ACC) User Interface 50.7.1 ACC Control Register 50.7.2 ACC Mode Register 50.7.3 ACC Interrupt Enable Register 50.7.4 ACC Interrupt Disable Register 50.7.5 ACC Interrupt Mask Register 50.7.6 ACC Interrupt Status Register 50.7.7 ACC Analog Control Register 50.7.8 ACC Write Protection Mode Register 50.7.9 ACC Write Protection Status Register 51. Integrity Check Monitor (ICM) 51.1 Description 51.2 Embedded Characteristics 51.3 Block Diagram 51.4 Product Dependencies 51.4.1 Power Management 51.4.2 Interrupt Sources 51.5 Functional Description 51.5.1 Overview 51.5.2 ICM Region Descriptor Structure 51.5.2.1 ICM Region Start Address Structure Member 51.5.2.2 ICM Region Configuration Structure Member 51.5.2.3 ICM Region Control Structure Member 51.5.2.4 ICM Region Next Address Structure Member 51.5.3 ICM Hash Area 51.5.3.1 Message Digest Example 51.5.4 Using ICM as SHA Engine 51.5.4.1 Settings for Simple SHA Calculation 51.5.4.2 Processing Period 51.5.5 ICM Automatic Monitoring Mode 51.5.6 Programming the ICM for Multiple Regions 51.5.7 Security Features 51.6 Integrity Check Monitor (ICM) User Interface 51.6.1 ICM Configuration Register 51.6.2 ICM Control Register 51.6.3 ICM Status Register 51.6.4 ICM Interrupt Enable Register 51.6.5 ICM Interrupt Disable Register 51.6.6 ICM Interrupt Mask Register 51.6.7 ICM Interrupt Status Register 51.6.8 ICM Undefined Access Status Register 51.6.9 ICM Descriptor Area Start Address Register 51.6.10 ICM Hash Area Start Address Register 51.6.11 ICM User Initial Hash Value Register 52. True Random Number Generator (TRNG) 52.1 Description 52.2 Embedded Characteristics 52.3 Block Diagram 52.4 Product Dependencies 52.4.1 Power Management 52.4.2 Interrupt 52.5 Functional Description 52.6 True Random Number Generator (TRNG) User Interface 52.6.1 TRNG Control Register 52.6.2 TRNG Interrupt Enable Register 52.6.3 TRNG Interrupt Disable Register 52.6.4 TRNG Interrupt Mask Register 52.6.5 TRNG Interrupt Status Register 52.6.6 TRNG Output Data Register 53. Advanced Encryption Standard (AES) 53.1 Description 53.2 Embedded Characteristics 53.3 Product Dependencies 53.3.1 Power Management 53.3.2 Interrupt 53.4 Functional Description 53.4.1 AES Register Endianism 53.4.2 Operation Modes 53.4.3 Double Input Buffer 53.4.4 Start Modes 53.4.4.1 Manual Mode 53.4.4.2 Auto Mode 53.4.4.3 DMA Mode 53.4.5 Last Output Data Mode 53.4.5.1 Manual and Auto Modes If AES_MR.LOD = 0 If AES_MR.LOD = 1 53.4.5.2 DMA Mode If AES_MR.LOD = 0 If AES_MR.LOD = 1 53.4.6 Galois/Counter Mode (GCM) 53.4.6.1 Description 53.4.6.2 Key Writing and Automatic Hash Subkey Calculation 53.4.6.3 GCM Processing Processing a Complete Message with Tag Generation Processing a Complete Message without Tag Generation Processing a Fragmented Message without Tag Generation Manual GCM Tag Generation Processing a Message with only AAD (GHASHH) Processing a Single GF128 Multiplication 53.4.7 Security Features 53.4.7.1 Countermeasures 53.4.7.2 Unspecified Register Access Detection 53.5 Advanced Encryption Standard (AES) User Interface 53.5.1 AES Control Register 53.5.2 AES Mode Register 53.5.3 AES Interrupt Enable Register 53.5.4 AES Interrupt Disable Register 53.5.5 AES Interrupt Mask Register 53.5.6 AES Interrupt Status Register 53.5.7 AES Key Word Register x 53.5.8 AES Input Data Register x 53.5.9 AES Output Data Register x 53.5.10 AES Initialization Vector Register x 53.5.11 AES Additional Authenticated Data Length Register 53.5.12 AES Plaintext/Ciphertext Length Register 53.5.13 AES GCM Intermediate Hash Word Register x 53.5.14 AES GCM Authentication Tag Word Register x 53.5.15 AES GCM Encryption Counter Value Register 53.5.16 AES GCM H Word Register x 54. Electrical Characteristics 54.1 Absolute Maximum Ratings 54.2 DC Characteristics 54.3 Power Consumption 54.3.1 Backup Mode Current Consumption and Wake-Up Time 54.3.1.1 Configuration A: Embedded Slow Clock RC Oscillator Enabled 54.3.1.2 Configuration B: 32.768 kHz Crystal Oscillator Enabled 54.3.1.3 Wake-up Time to Resume from Backup Mode 54.3.2 Sleep Mode Current Consumption and Wake-up Time 54.3.3 Wait Mode Current Consumption and Wake-up Time 54.3.4 Active Mode Power Consumption 54.3.5 Peripheral Power Consumption in Active Mode 54.3.6 I/O Switching Power Consumption 54.4 Oscillator Characteristics 54.4.1 32 kHz RC Oscillator Characteristics 54.4.2 4/8/12 MHz RC Oscillators Characteristics 54.4.3 32.768 kHz Crystal Oscillator Characteristics 54.4.4 32.768 kHz Crystal Characteristics 54.4.5 3 to 20 MHz Crystal Oscillator Characteristics 54.4.6 3 to 20 MHz Crystal Characteristics 54.4.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode 54.4.8 Crystal Oscillator Design Considerations 54.4.8.1 Choosing a Crystal 54.4.8.2 Printed Circuit Board (PCB) 54.5 PLLA Characteristics 54.6 PLLUSB Characteristics 54.7 USB Transceiver Characteristics 54.7.1 Electrical Characteristics 54.7.2 Static Power Consumption 54.7.3 Dynamic Power Consumption 54.8 AFE Characteristics 54.8.1 AFE Power Supply 54.8.1.1 Power Supply Characteristics 54.8.1.2 ADC Bias Current 54.8.2 External Reference Voltage 54.8.3 AFE Timings 54.8.4 AFE Transfer Function 54.8.4.1 Differential Mode (12-bit mode) 54.8.4.2 Single-ended Mode (12-bit mode) 54.8.4.3 Example of LSB Computation 54.8.5 AFE Electrical Characteristics 54.8.5.1 Gain and Offset Errors Differential Mode Single-ended Mode 54.8.5.2 AFE Electrical Performances Single-ended Static Performances Single-ended Dynamic Performances Differential Static Performances Differential Dynamic Performances 54.8.6 AFE Channel Input Impedance Track and Hold Time versus Source Output Impedance 54.8.6.1 AFE DAC Offset Compensation 54.8.7 AFE Resolution with Averaging 54.8.7.1 Conditions at 25°C with Gain = 1 54.8.7.2 Conditions at 25°C with Gain = 4 54.9 Analog Comparator Characteristics 54.10 Temperature Sensor 54.11 12-bit DAC Characteristics 54.12 Timings for Worst-Case Conditions 54.12.1 AC Characteristics 54.12.1.1 Processor Clock Characteristics 54.12.1.2 Master Clock Characteristics 54.12.1.3 I/O Characteristics 54.12.1.4 QSPI Characteristics Maximum QSPI Frequency Master Write Mode Master Read Mode QSPI Timings 54.12.1.5 SPI Characteristics Maximum SPI Frequency Master Write Mode Master Read Mode Slave Read Mode Slave Write Mode SPI Timings 54.12.1.6 HSMCI Timings 54.12.1.7 SDRAM Timings 54.12.1.8 SMC Timings Read Timings Write Timings 54.12.1.9 USART in SPI Mode Timings USART SPI TImings 54.12.1.10 Two-wire Serial Interface Characteristics 54.12.1.11 GMAC Characteristics Timing Conditions Timing Constraints MII Mode RMII Mode 54.12.1.12 SSC Timings Timing Conditions Timing Extraction 54.12.1.13 ISI Timings Timing Conditions Timing Extraction 54.12.2 Embedded Flash Characteristics 54.13 Timings for STH Conditions 54.13.1 AC Characteristics 54.13.1.1 Processor Clock Characteristics 54.13.1.2 Master Clock Characteristics 54.13.1.3 I/O Characteristics 54.13.1.4 QSPI Characteristics Maximum QSPI Frequency Master Write Mode Master Read Mode QSPI Timings 54.13.1.5 SPI Characteristics Maximum SPI Frequency Master Write Mode Master Read Mode Slave Read Mode Slave Write Mode SPI Timings 54.13.1.6 HSMCI Timings 54.13.1.7 SDRAM Timings 54.13.1.8 SMC Timings Read Timings Write Timings 54.13.1.9 USART in SPI Mode Timings USART SPI TImings 54.13.1.10 Two-wire Serial Interface Characteristics 54.13.1.11 GMAC Characteristics Timing Conditions Timing Constraints MII Mode RMII Mode 54.13.1.12 SSC Timings Timing Conditions Timing Extraction 54.13.1.13 ISI Timings Timing Conditions Timing Extraction 54.13.2 Embedded Flash Characteristics 55. Mechanical Characteristics 55.1 144-pin LQFP Package 55.2 144-ball LFBGA Package 55.3 100-pin LQFP Package 55.4 100-ball TFBGA Package 55.5 64-pin LQFP Package 55.6 Soldering Profile 55.7 Packaging Resources 56. Marking 57. Ordering Information 58. Revision History Table of Contents